TPS7A7002DDAR
Public Unreviewedby Ray
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8-EP. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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README
markdownTPS7A7002DDAR
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOIC-8-EP
TPS7A7002DDAR from Texas Instruments, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | Not internally connected. TI recommends connecting NC pins to large-area planes. |
| 2 | EN | input | Enable input. Pulling this pin to less than 0.5 V turns the regulator off; pulling it to at least 1.1 V enables it. Connect to VIN if not being used. VEN range 0 V to VIN; IEN typ 0.2 µA max. |
| 3 | IN | power_in | Input supply pin, 1.425 V to 6.5 V. Although not required for stability, TI recommends a 1-µF to 10-µF low-ESR capacitor from IN to GND. |
| 4 | NC | unconnected | Not internally connected. TI recommends connecting NC pins to large-area planes. |
| 5 | NC | unconnected | Not internally connected. TI recommends connecting NC pins to large-area planes. |
| 6 | OUT | power_out | Regulated output, adjustable from 0.5 V, supplying up to 3 A. A 4.7-µF or larger capacitor of any type is required for stability (4.7 µF to 200 µF recommended range). |
| 7 | FB | input | Output-voltage feedback input. Connect to the tap of an external R1/R2 divider from OUT to GND; VOUT = 0.5 × (1 + R1/R2). VREF nominal 0.5 V; IFB max 1 µA. Use 27-kΩ ≤ R2 ≤ 33-kΩ when setting VOUT above 0.5 V. |
| 8 | GND | power_in | Ground reference pin. IGND typical 3 mA (VIN = 3.3 V, 50-Ω load); shutdown IGND max 5 µA. |
| 9 | PowerPAD | passive | Exposed thermal pad on the package underside. TI strongly recommends connecting to a large-area ground plane; may alternatively connect to an electrically floating dedicated thermal plane. Required for the specified 46.4 °C/W RθJA thermal performance. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8-EP |
| Category | PMIC |
| Pins | 9 |
Ordering variants
Same part, different packaging or reel option.
TPS7A7002DDAR
CAD (KiCad official)
- Symbol:
TPS7A7002DDAR - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOIC-8-EP (KiCad packages3D, STEP)
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
tps7a7002ddar.step |
125 KB | You want the bare part, or you mark your own boards. |
tps7a7002ddar-etched.step |
2.4 MB | You want the part with TPS7A7002DDAR already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 605 faces against 152 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (21 pp, sha256
c599367c7bc6a7fc, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).