TPS74401RGWR from Texas Instruments, in a VQFN-20-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OUT	power_out	Regulated output. Tied together with pins 18-20. Adjustable 0.8-3.6 V, up to 3 A. Output capacitor not required for stability but recommended for optimal performance.
2	NC	unconnected	No connection. May be left floating or tied to GND to improve thermal contact to the top-side plane.
3	NC	unconnected	No connection. May be left floating or tied to GND for improved thermal contact.
4	NC	unconnected	No connection. May be left floating or tied to GND for improved thermal contact.
5	IN	power_in	Unregulated input supply. Pins 5-8 tied together. Range 1.1-5.5 V. A 1 µF (or 4.7 µF if IN=BIAS) input capacitor is recommended.
6	IN	power_in	Unregulated input supply. Tied with pins 5, 7, 8.
7	IN	power_in	Unregulated input supply. Tied with pins 5, 6, 8.
8	IN	power_in	Unregulated input supply. Tied with pins 5, 6, 7.
9	PG	output	Power-good open-drain, active-high output indicating VOUT status. High-Z when VOUT exceeds the PG trip threshold, low when below. Requires a 10 kΩ-1 MΩ pull-up to a supply up to 5.5 V (may exceed VIN).
10	BIAS	power_in	Bias input voltage for the error amplifier, reference, and internal control. Range VOUT+VDO(BIAS) to 5.5 V. A 1 µF (or 4.7 µF if tied to IN) bias capacitor is recommended.
11	EN	input	Active-high enable. Driving high enables the regulator; driving low puts the device into shutdown. Must not be left floating. 0-5.5 V range.
12	GND	power_in	Device ground. Internally connected to the exposed thermal pad.
13	NC	unconnected	No connection. May be left floating or tied to GND for improved thermal contact.
14	NC	unconnected	No connection. May be left floating or tied to GND for improved thermal contact.
15	SS	passive	Soft-start programming pin. A capacitor from SS to GND sets the linear output ramp time. If left floating the soft-start ramp is typically 100 µs.
16	FB	input	Feedback input to the internal error amplifier. Connect to the center tap of an external R1/R2 divider to set VOUT (VOUT = VREF × (1 + R1/R2)). Must not be left floating.
17	NC	unconnected	No connection. May be left floating or tied to GND for improved thermal contact.
18	OUT	power_out	Regulated output. Tied together with pins 1, 19, 20.
19	OUT	power_out	Regulated output. Tied together with pins 1, 18, 20.
20	OUT	power_out	Regulated output. Tied together with pins 1, 18, 19.
21	PAD	power_in	Exposed thermal pad on the package underside. Internally connected to GND. Must be soldered to the ground plane for proper thermal performance.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-20-EP(5x5)
Category	PMIC
Pins	21

Ordering variants

Same part, different packaging or reel option.

TPS74401RGWR
TPS74401RGWRRGWT
TPS74401RGWRRGRR
TPS74401RGWRRGRT
TPS74401RGWRKTWR
TPS74401RGWRKTWT

CAD (KiCad official)

Symbol: TPS74401RGWR
Footprint: Package_DFN_QFN:QFN-20-1EP_5x5mm_P0.65mm_EP3.35x3.35mm
3D model: VQFN-20-EP(5x5) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (40 pp, sha256 836a1368a0a62bcd, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF