TPS65100RGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	COMP	passive	Compensation pin for the main boost converter loop. A small compensation capacitor (and optional series R) is connected from this pin to GND to set the loop bandwidth.
2	ENR	input	Enable pin of the auxiliary 3.3 V linear regulator controller. Logic high enables the LDO controller, logic low forces it into shutdown. Must be terminated, not left floating (VIH ≥ 1.5 V, VIL ≤ 0.4 V, referenced to VIN).
3	EN	input	Master enable pin for the device. Logic high enables the TPS6510x, logic low shuts the device down. Must be terminated, not left floating (VIH ≥ 1.5 V, VIL ≤ 0.4 V, referenced to VIN).
4	FB1	input	Feedback pin of the main boost converter (VO1). External resistor divider from VO1 sets the output voltage; regulates to the 1.146 V (typ) internal reference.
5	FB4	input	Feedback pin of the auxiliary 3.3 V linear regulator controller. Regulates the external pass-transistor output to a fixed 3.3 V (or 3 V depending on device version).
6	BASE	output	Base drive output for the external pass transistor of the 3.3 V linear regulator controller. If the linear regulator is not needed, tie this pin to VIN.
7	VIN	power_in	Input supply pin of the device. 2.7 V to 5.8 V operating range; UVLO trips at ~2.4 V (falling). Decouple locally to GND.
8	SW	passive	Switch node of the internal boost converter (drain of the internal N-MOSFET / source of the internal P-MOSFET). Connect to the boost inductor. Pin 8 and pin 9 are internally tied and must be paralleled externally. Rated to 20 V absolute max.
9	SW	passive	Switch node of the internal boost converter (paralleled with pin 8). Connect to the boost inductor. Rated to 20 V absolute max.
10	PGND	power_in	Power ground return for the boost converter power stage. Pin 10 and pin 11 must be paralleled externally and tied to the exposed thermal die.
11	PGND	power_in	Power ground return for the boost converter power stage (paralleled with pin 10). Must be tied to the exposed thermal die.
12	SUP	power_in	Supply pin for the positive and negative charge pumps, boost gate drive circuit and VCOM buffer. Must be connected to the main boost converter output (VO1) and to no other source. Rated to 15.5 V max; TI recommends no local bypass capacitor directly on this pin.
13	VCOM	output	Output of the integrated VCOM buffer used to drive the LCD backplane. Powered from SUP.
14	VCOMIN	input	Positive (non-inverting) input of the VCOM buffer. Tie to GND when the VCOM buffer is unused to reduce quiescent current. Absolute max 14 V.
15	FB3	input	Feedback pin of the positive charge pump output (VO3). External resistor divider from OUT3 sets the regulated positive gate-drive voltage.
16	OUT3	power_out	Positive charge pump output (VO3), up to 30 V / 20 mA. Provides the positive LCD gate-drive voltage.
17	C2+	passive	Positive terminal of the second charge-pump flying capacitor. Leave open when the positive charge pump operates in voltage-doubler mode.
18	C2-/MODE	passive	Dual-function pin: negative terminal of the second flying capacitor and charge-pump MODE select. Connecting a flying cap between C2+ and C2-/MODE selects voltage-tripler mode; removing the cap and tying this pin to GND selects voltage-doubler mode.
19	C1+	passive	Positive terminal of the first charge-pump flying capacitor.
20	C1-	passive	Negative terminal of the first charge-pump flying capacitor.
21	DRV	output	External charge-pump driver output. Drives the external diodes/capacitors that generate the regulated negative rail VO2 (down to -12 V / 20 mA). Rated to 15 V max.
22	GND	power_in	Analog/signal ground for the device.
23	REF	output	Internal reference output, typically 1.213 V (1.205-1.219 V). Bypass to GND with a small capacitor; not intended to source external loads.
24	FB2	input	Feedback pin of the negative charge pump (VO2). External resistor divider between a positive reference and the negative output sets the regulated negative gate-drive voltage.
PAD	EP	power_in	Exposed thermal die (PowerPAD) on the underside of the VQFN package. Must be soldered to the PCB and connected to the power ground pins (PGND) for both electrical return and heat sinking.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-24-EP(4x4)
Category	LED Drivers
Pins	25

Ordering variants

Same part, different packaging or reel option.

TPS65100RGER
TPS65100RGERRGET
TPS65100RGERPWP
TPS65100RGERPWPR

CAD (KiCad official)

Symbol: TPS65100RGER
Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm
3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (None pp, sha256 2bf67383027da5b0, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF