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TPS62133RGTR

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by Ray

Texas Instruments DC-DC Converters, VQFN-16-EP(3x3). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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TPS62133RGTR

Texas Instruments · DC-DC Converters · VQFN-16-EP(3x3)

TPS62133RGTR from Texas Instruments, in a VQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SW output Switch node connected to the internal high-side and low-side MOSFETs. Connect an inductor between SW and the output capacitor. Pins 1, 2, and 3 are tied together internally and must all be connected.
2 SW output Switch node connected to the internal MOSFET switches. Connect an inductor between SW and the output capacitor.
3 SW output Switch node connected to the internal MOSFET switches. Connect an inductor between SW and the output capacitor.
4 PG output Open-drain power-good output. High = VOUT ready; Low = VOUT below nominal regulation. Requires an external pull-up resistor. Maximum sink current 10 mA; VOL ≈ 0.07 V at IPG = 2 mA.
5 FB input Voltage feedback pin for the adjustable version. Connect a resistive voltage divider to this pin. For fixed-output versions (such as TPS62133), tie FB to AGND for improved thermal performance.
6 AGND power_in Analog ground. Must be connected directly to the Exposed Thermal Pad and to the common ground plane.
7 FSW input Switching frequency select. Low ≈ 2.5 MHz, High ≈ 1.25 MHz (typical). Connect FSW to VOUT or PG in this case. An internal pull-down keeps the pin low if floating.
8 DEF input Output voltage scaling. Low = nominal output, High = nominal + 5%. Internal pull-down keeps the pin low if floating.
9 SS/TR input Soft-start / tracking pin. An external capacitor sets the internal voltage reference rise time. Can be driven for tracking/sequencing. Source current ISS/TR ≈ 2.5 µA.
10 AVIN power_in Supply voltage for the control circuitry. Must be connected to the same source as PVIN. Input voltage range 3 V to 17 V (absolute max 20 V).
11 PVIN power_in Supply voltage for the power stage. Must be connected to the same source as AVIN. Input voltage range 3 V to 17 V (absolute max 20 V). Pins 11 and 12 are tied together internally.
12 PVIN power_in Supply voltage for the power stage. Must be connected to the same source as AVIN.
13 EN input Enable input. High = enabled, Low = disabled. Internal pull-down keeps logic level low if pin is floating. VH ≈ 0.9 V, VL ≈ 0.45 V.
14 VOS input Output voltage sense pin and connection for the control-loop circuitry. Connect to the regulated output node.
15 PGND power_in Power ground. Must be connected directly to the Exposed Thermal Pad and to the common ground plane.
16 PGND power_in Power ground. Must be connected directly to the Exposed Thermal Pad and to the common ground plane.
17 EP power_in Exposed Thermal Pad. Must be connected to AGND (pin 6), PGND (pins 15, 16), and the common ground plane. Must be soldered to achieve appropriate power dissipation and mechanical reliability.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-16-EP(3x3)
Category PMIC
Pins 17

Ordering variants

Same part, different packaging or reel option.

  • TPS62133RGTR
  • TPS62133RGTRRGTT

CAD (KiCad official)

  • Symbol: TPS62133RGTR
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: VQFN-16-EP(3x3) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (43 pp, sha256 8123e7da5ae64959, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF