TPS62132RGTT from Texas Instruments, in a VQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SW	output	Switch node connected to the internal high-side/low-side MOSFETs. Tie pins 1-3 together and connect the external power inductor (typically 1 µH or 2.2 µH) between SW and the output capacitor.
2	SW	output	Switch node (parallel with pins 1 and 3). Tie all SW pins together for current handling and connect the external power inductor between SW and the output capacitor.
3	SW	output	Switch node (parallel with pins 1 and 2). All three SW pins must be tied together on the PCB and routed to the inductor.
4	PG	output	Power-good output, open-drain (requires a pull-up resistor, typically 100 kΩ to VOUT or an external logic rail). Logic High indicates VOUT is in regulation; logic Low indicates VOUT is below the nominal regulation threshold. Max sink current 10 mA.
5	FB	input	Feedback pin for the adjustable version. On this fixed 3.3-V TPS62132, the datasheet recommends tying FB directly to AGND for improved thermal performance (internal feedback is used).
6	AGND	power_in	Analog ground reference for the control circuitry. Must be tied directly to the exposed thermal pad and the common ground plane.
7	FSW	input	Switching-frequency select. Low (or floating with internal pull-down) ≈ 2.5 MHz nominal; High ≈ 1.25 MHz nominal. Tie to VOUT or PG when selecting 1.25 MHz operation.
8	DEF	input	Output-voltage scaling / default-select input. Low = nominal VOUT (3.3 V); High = nominal + 5%. Internal pull-down keeps DEF low if floating.
9	SS/TR	input	Soft-start and tracking input. An external capacitor (e.g. 3.3 nF) to AGND sets the ramp rate of the internal reference; can also be driven for tracking/sequencing of the output with an external reference.
10	AVIN	power_in	Supply voltage for the internal control circuitry, 3 V to 17 V. Must be connected to the same source as PVIN; decouple locally (typically 0.1 µF to AGND).
11	PVIN	power_in	Power-stage input supply, 3 V to 17 V. Tie pins 11 and 12 together and connect to the same rail as AVIN; place the input capacitor (typically 10 µF) close to these pins.
12	PVIN	power_in	Power-stage input supply (parallel with pin 11). Both PVIN pins must be tied together on the PCB.
13	EN	input	Enable input. High = converter enabled; Low = shutdown (device draws <2 µA, typ 1.5 µA). Internal pull-down keeps EN low if floating.
14	VOS	input	Output-voltage sense pin for the internal control loop. Connect directly to the regulated output rail (VOUT) at the output capacitor.
15	PGND	power_in	Power ground return for the internal low-side MOSFET. Must be connected directly to the exposed thermal pad and the common ground plane.
16	PGND	power_in	Power ground return (parallel with pin 15). Tie both PGND pins to the exposed thermal pad and ground plane.
17	EP	power_in	Exposed thermal pad on the package bottom. Must be soldered to the PCB and connected to AGND (pin 6), PGND (pins 15/16), and the common ground plane for both electrical return and thermal dissipation.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-16-EP(3x3)
Category	Power Supply Chip
Pins	17

Ordering variants

Same part, different packaging or reel option.

TPS62132RGTTRGTR
TPS62132RGTT

CAD (KiCad official)

Symbol: TPS62132RGTT
Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
3D model: VQFN-16-EP(3x3) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (None pp, sha256 f11a6a1cc73d8ec2, retrieved 2026-08-17, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF