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TPS54386PWPR

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by Ray

Texas Instruments AC-DC Controllers and Regulators, HTSSOP-14-EP. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

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TPS54386PWPR

Texas Instruments · AC-DC Controllers and Regulators · HTSSOP-14-EP

TPS54386PWPR from Texas Instruments, in a HTSSOP-14-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PVDD1 power_in Power input to the Output 1 high-side MOSFET only. Should be locally bypassed to GND with a low-ESR ceramic capacitor of 10 µF or greater. Input voltage range 4.5 V to 28 V (abs max 30 V).
2 BOOT1 input Bootstrap input supply to the Output 1 high-side gate driver. Connect a 22-nF to 82-nF capacitor from this pin to SW1; charged from BP through an internal switch during the OFF time. A 1-Ω to 3-Ω series resistor may be added to slow FET turn-on. Abs max V(SW)+7 V.
3 SW1 output Source (switching) output for Output 1 PWM. Connects to the external inductor and catch diode. A snubber is recommended to reduce ringing. Abs max -2 V to 30 V (-3 V transient <50 ns).
4 GND power_in Ground pin for the device. Connect directly to the Thermal Pad.
5 EN1 input Active-low enable input for Output 1. If the voltage on this pin is greater than 1.55 V, Output 1 is disabled (high-side switch is OFF); a voltage less than 0.9 V enables Output 1 and allows soft-start to begin. An internal current source drives this pin to PVDD2 if left floating. Tie to GND for always-on operation.
6 EN2 input Active-low enable input for Output 2. If the voltage on this pin is greater than 1.55 V, Output 2 is disabled (high-side switch is OFF); a voltage less than 0.9 V enables Output 2 and allows soft-start to begin. An internal current source drives this pin to PVDD2 if left floating. Tie to GND for always-on operation.
7 FB1 input Voltage feedback pin for Output 1. Internal transconductance error amplifier regulates this pin to the 0.8-V reference. A series resistor divider from Output 1 to GND sets the output voltage; loop compensation is internal. Abs max -0.3 V to 3 V.
8 FB2 input Voltage feedback pin for Output 2. Internal transconductance error amplifier regulates this pin to the 0.8-V reference. A series resistor divider from Output 2 to GND sets the output voltage; loop compensation is internal. Abs max -0.3 V to 3 V.
9 ILIM2 input Current-limit adjust pin for Output 2 only. Allows asymmetrical scaling of Output 2 current limit (three selectable levels) via strapping to BP, GND, or float. An internal 2-resistor divider (150 kΩ each) connects BP to ILIM2 and to GND. Abs max -0.3 V to 6.5 V.
10 SEQ input Startup-mode configuration pin. Tie to BP for Output 1 slave to Output 2 sequential startup; tie to GND for Output 2 slave to Output 1 sequential startup; leave floating for ratiometric simultaneous startup with independent operation. An internal 150-kΩ/150-kΩ divider connects BP to SEQ and to GND. Abs max -0.3 V to 6.5 V.
11 BP power_out Internally regulated voltage that charges the bootstrap capacitors and biases internal circuitry. Bypass to GND with a low-ESR 4.7-µF to 10-µF X7R or X5R ceramic capacitor. Abs max 6.5 V; load current 35 mA max.
12 SW2 output Source (switching) output for Output 2 PWM. Connects to the external inductor and catch diode. A snubber is recommended to reduce ringing. Abs max -2 V to 30 V (-3 V transient <50 ns).
13 BOOT2 input Bootstrap input supply to the Output 2 high-side gate driver. Connect a 22-nF to 82-nF capacitor from this pin to SW2; charged from BP through an internal switch during the OFF time. A 1-Ω to 3-Ω series resistor may be added to slow FET turn-on. Abs max V(SW)+7 V.
14 PVDD2 power_in Provides power to the device control circuitry, pull-up for the EN1/EN2 pins, and power to the Output 2 high-side MOSFET. Bypass locally to GND with a low-ESR 10-µF or greater ceramic capacitor. UVLO enables the device when PVDD2 is greater than 4.1 V. Input voltage range 4.5 V to 28 V (abs max 30 V).
15 PAD power_in Exposed thermal pad on the bottom side of the package. Must be tied externally to a ground plane and to the GND pin (pin 4) for proper thermal performance and electrical grounding.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-14-EP
Category PMIC
Pins 15

Ordering variants

Same part, different packaging or reel option.

  • TPS54386PWPR

CAD (KiCad official)

  • Symbol: TPS54386PWPR
  • Footprint: Package_SO:TSSOP-14-1EP_4.4x5mm_P0.65mm
  • 3D model: HTSSOP-14-EP (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (56 pp, sha256 900e7d81bc6ecc02, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF