TPS54360BDDAR from Texas Instruments, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	BOOT	passive	Bootstrap capacitor node for the high-side MOSFET gate driver. A bootstrap capacitor is required between BOOT and SW. If the voltage on this capacitor falls below the minimum required to operate the high-side MOSFET, the output is switched off until the capacitor is refreshed. BOOT-SW max 8 V; BOOT abs max 73 V.
2	VIN	power_in	Input supply voltage, 4.5 V to 60 V operating range (65 V absolute max). Bypass with a low-ESR ceramic capacitor placed close to the pin.
3	EN	input	Enable pin with internal pull-up current source. Pull below 1.2 V to disable; float to enable. Adjust the input undervoltage lockout with two resistors. Abs max 8.4 V; typical enable threshold 1.2 V.
4	RT/CLK	bidirectional	Resistor Timing and External Clock input. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency (100 kHz to 2.5 MHz). If pulled above the PLL upper threshold (~2 V) the pin becomes a synchronization input to the internal PLL. Abs max 3.6 V.
5	FB	input	Inverting input of the transconductance (gm) error amplifier. Connect the output feedback divider from VOUT to FB and GND (0.8 V ±1% internal reference).
6	COMP	output	Error amplifier output and input to the output switch current (PWM) comparator. Connect the frequency compensation network (Type-II RC) between COMP and GND. Abs max 3 V.
7	GND	power_in	Device ground. Must be electrically connected to the exposed thermal pad on the PCB for proper operation.
8	SW	power_out	Source of the internal high-side power MOSFET and switching node of the converter. Connect to the output inductor and catch diode. Abs max −0.6 V to 65 V (−2 V for 10-ns transients).
9	PAD	power_in	Exposed thermal PowerPAD on the package bottom. Must be electrically connected to GND (pin 7) on the PCB for proper electrical and thermal operation. Provides the primary heat-sink path (Rθ J-C(bot) = 3.6 °C/W).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-8-EP
Category	PMIC
Pins	9

Ordering variants

Same part, different packaging or reel option.

TPS54360BDDAR

CAD (KiCad official)

Symbol: TPS54360BDDAR
Footprint: Package_SO:TI_SO-PowerPAD-8
3D model: SOIC-8-EP (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`tps54360bddar.step`	123 KB	You want the bare part, or you mark your own boards.
`tps54360bddar-etched.step`	2.8 MB	You want the part with `TPS54360BDDAR` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 689 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (46 pp, sha256 2f01aef8076509ce, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF