component
TPS54331DDAR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, SOIC-8-EP. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownTPS54331DDAR
Texas Instruments · DC-DC Converters · SOIC-8-EP
TPS54331DDAR from Texas Instruments, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | output | Bootstrap capacitor node for the internal high-side MOSFET gate driver. A 0.1-µF capacitor is required between BOOT and PH. If the BOOT-PH voltage falls below the minimum requirement, the high-side MOSFET is forced off until the capacitor is refreshed. Absolute max BOOT: 38 V; BOOT-PH: 8 V. |
| 2 | VIN | power_in | Input supply voltage pin, 3.5 V to 28 V recommended operating range (absolute max 30 V). Bypass close to the pin with a low-ESR ceramic capacitor. |
| 3 | EN | input | Enable input. Pull below 1.25 V to disable the converter; float to enable. May be driven from a resistor divider off VIN to program input UVLO. Absolute max 6 V. |
| 4 | SS | input | Slow-start pin. An external capacitor from SS to GND sets the output-voltage rise time, limiting inrush current during startup. |
| 5 | VSENSE | input | Inverting input of the internal transconductance (gm) error amplifier. Connected via the output-voltage feedback divider; the amplifier regulates VSENSE to the internal 0.8-V reference. |
| 6 | COMP | output | Error-amplifier output and PWM comparator input. Connect the frequency-compensation network (typically a series R-C plus optional high-frequency pole cap) between COMP and GND. |
| 7 | GND | power_in | Device ground. On the DDA package this pin must also be connected to the exposed PowerPAD for proper thermal and electrical operation. |
| 8 | PH | output | Switch node: source of the internal high-side power MOSFET. Connect to the inductor and to the cathode of the external freewheeling (catch) diode. Handles up to ~9-A source/sink transient current. |
| 9 | PowerPAD | power_in | Exposed thermal pad on the DDA package only. Must be connected to the GND pin (pin 7) and soldered to a PCB ground plane for proper electrical and thermal performance. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8-EP |
| Category | PMIC |
| Pins | 9 |
Ordering variants
Same part, different packaging or reel option.
TPS54331DDARTPS54331DDARDTPS54331DDARDR
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage (VIN pin) | -0.3 | 30 | V | 5 | |||
| Input voltage (EN pin) | -0.3 | 6 | V | 5 | |||
| Input voltage (BOOT pin) | 38 | V | 5 | ||||
| Input voltage (VSENSE pin) | -0.3 | 3 | V | 5 | |||
| Voltage (COMP pin) | -0.3 | 3 | V | 5 | |||
| Voltage (SS pin) | -0.3 | 3 | V | 5 | |||
| BOOT-PH voltage | 8 | V | 5 | ||||
| Output voltage (PH pin) | -0.6 | 30 | V | 5 | |||
| PH pin negative transient | -5 | V | 10-ns transient from ground to negative peak | 5 | |||
| Source current (EN pin) | 100 | μA | 5 | ||||
| Source current (BOOT pin) | 100 | mA | 5 | ||||
| Source current (VSENSE pin) | 10 | μA | 5 | ||||
| Source current (PH pin) | 9 | A | 5 | ||||
| Source current (VIN pin) | 9 | A | 5 | ||||
| Sink current (COMP pin) | 100 | μA | 5 | ||||
| Sink current (SS pin) | 200 | μA | 5 | ||||
| Operating junction temperature (absolute maximum) | TJ | -40 | 150 | °C | 5 | ||
| Operating input voltage (VIN pin) | 3.5 | 28 | V | 5 | |||
| Operating junction temperature (recommended) | TJ | -40 | 150 | °C | 5 | ||
| Shutdown supply current | 1 | 4 | μA | EN = 0V, VIN = 12V, –40°C to 85°C | 6 | ||
| Internal undervoltage lockout threshold | 3.5 | V | Rising and falling | 6 | |||
| Operating non-switching supply current | 110 | 190 | μA | VSENSE = 0.85 V | 6 | ||
| Enable threshold | 1.25 | 1.35 | V | Rising and falling | 6 | ||
| Voltage reference | 0.772 | 0.8 | 0.828 | V | 6 | ||
| High-side MOSFET on resistance | 115 | 200 | mΩ | BOOT-PH = 3 V, VIN = 3.5 V | 6 | ||
| High-side MOSFET on resistance | 80 | 150 | mΩ | BOOT-PH = 6 V, VIN = 12 V | 6 | ||
| Error amplifier source/sink current | -7 | 7 | μA | V(COMP) = 1 V, 100-mV overdrive | 6 | ||
| Current-limit threshold | 3.5 | 5.8 | A | VIN = 12 V | 6 | ||
| Switching frequency | 456 | 570 | 684 | kHz | VIN = 12 V, 25°C | 7 | |
| Minimum controllable on time | 105 | 130 | ns | VIN = 12 V, 25°C | 7 | ||
| Maximum controllable duty ratio | 90 | 93 | % | BOOT-PH = 6 V | 7 | ||
| Input current at enable threshold – 50 mV | -1 | μA | Enable threshold – 50 mV | 6 | |||
| Input current at enable threshold + 50 mV | -4 | μA | Enable threshold + 50 mV | 6 | |||
| Error amplifier transconductance (gm) | gm | 92 | μmhos | –2 μA < I(COMP) < 2 μA, V(COMP) = 1 V | 6 | ||
| Error amplifier DC gain | 800 | V/V | VSENSE = 0.8 V | 6 | |||
| Error amplifier unity gain bandwidth | 2.7 | MHz | 5-pF capacitance from COMP to GND pins | 6 | |||
| Switch current to COMP transconductance | 12 | A/V | VIN = 12 V | 6 | |||
| Pulse skipping Eco-mode switch current threshold | 160 | mA | 6 | ||||
| Thermal shutdown | 165 | °C | 6 | ||||
| SS charge current | 2 | μA | V(SS) = 0.4 V | 6 | |||
| SS to VSENSE matching | 10 | mV | V(SS) = 0.4 V | 6 | |||
| Junction-to-ambient thermal resistance (DDA) | RθJA | 48.7 | °C/W | DDA package | 6 | ||
| Junction-to-case (top) thermal resistance (DDA) | RθJC(top) | 52.4 | °C/W | DDA package | 6 | ||
| Junction-to-board thermal resistance (DDA) | RθJB | 25.5 | °C/W | DDA package | 6 | ||
| Junction-to-top characterization parameter (DDA) | ψJT | 8.4 | °C/W | DDA package | 6 | ||
| Junction-to-board characterization parameter (DDA) | ψJB | 25.2 | °C/W | DDA package | 6 | ||
| Junction-to-case (bottom) thermal resistance (DDA) | RθJC(bot) | 2.3 | °C/W | DDA package | 6 |
CAD (KiCad official)
- Symbol:
TPS54331DDAR - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files:
tps54331ddar-etched.step/tps54331ddar-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps54331ddar.step/tps54331ddar.glbare the bare package body.
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
tps54331ddar.step |
125 KB | You want the bare part, or you mark your own boards. |
tps54331ddar-etched.step |
2.5 MB | You want the part with TPS54331DDAR already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 616 faces against 152 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (36 pp, sha256
94afb96d8b709e87, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).