component
TPS51125RGER
Public Unreviewedby Ray
Texas Instruments DC-DC Converters, QFN-24-EP(4x4). Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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Datasheet
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README
markdownTPS51125RGER
Texas Instruments · DC-DC Converters · QFN-24-EP(4x4)
TPS51125RGER from Texas Instruments, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ENTRIP1 | bidirectional | Channel 1 enable and OCL trip setting pin. Connect a resistor from this pin to GND to set the threshold for synchronous RDS(on) current sense. Short to GND to shut down the channel 1 switcher. |
| 2 | VFB1 | input | SMPS feedback input for channel 1. Connect with a feedback resistor divider from the channel-1 output. |
| 3 | VREF | output | 2-V reference voltage output (1% accuracy). Connect a 220-nF to 1-µF ceramic capacitor to Signal GND near the device. |
| 4 | TONSEL | input | On-time adjustment (switching frequency select) pin. Connect to VREG5 for 365/460 kHz, VREG3 for 300/375 kHz, VREF for 245/305 kHz, or GND for 200/250 kHz operation. |
| 5 | VFB2 | input | SMPS feedback input for channel 2. Connect with a feedback resistor divider from the channel-2 output. |
| 6 | ENTRIP2 | bidirectional | Channel 2 enable and OCL trip setting pin. Connect a resistor from this pin to GND to set the threshold for synchronous RDS(on) current sense. Short to GND to shut down the channel 2 switcher. |
| 7 | VO2 | bidirectional | Output connection to SMPS channel 2. Works as a fixed voltage input and output discharge input, and as the 3.3-V switch-over return power input. |
| 8 | VREG3 | power_out | 3.3-V LDO power supply output. Connect a 10-µF ceramic capacitor to Power GND near the device (1-µF acceptable when unloaded). |
| 9 | VBST2 | power_in | Supply input for the channel-2 high-side N-channel MOSFET driver (bootstrap/boost terminal). Referenced to LL2, range -0.1 V to 5.5 V with respect to LL2. |
| 10 | DRVH2 | output | High-side N-channel MOSFET gate driver output for channel 2. Referenced to LL2. |
| 11 | LL2 | input | Channel-2 switch node connection for the high-side driver, current-limit sensing and control circuitry. |
| 12 | DRVL2 | output | Low-side N-channel MOSFET gate driver output for channel 2. GND referenced. |
| 13 | EN0 | bidirectional | Master enable input. Open: LDOs on and ready to enable VCLK and switcher channels. 620 kΩ to GND: enables both LDOs, VCLK off but ready to enable switchers. Short to GND: disables all circuits. |
| 14 | SKIPSEL | input | Selection pin for operating mode. Connect to VREG3 or VREG5 for OOA (Out-of-Audio) auto skip; connect to VREF for auto skip. |
| 15 | GND | power_in | Device ground reference for the control circuitry and low-side drivers. |
| 16 | VIN | power_in | High-voltage power supply input for the 5-V and 3.3-V LDOs. Operating range 5.5 V to 28 V (absolute max 30 V). |
| 17 | VREG5 | power_out | 5-V LDO power supply output. Connect a 33-µF ceramic capacitor to Power GND near the device. |
| 18 | VCLK | output | 270-kHz clock output used to drive an external 15-V charge pump for the load-switch gate drive. |
| 19 | DRVL1 | output | Low-side N-channel MOSFET gate driver output for channel 1. GND referenced. |
| 20 | LL1 | input | Channel-1 switch node connection for the high-side driver, current-limit sensing and control circuitry. |
| 21 | DRVH1 | output | High-side N-channel MOSFET gate driver output for channel 1. Referenced to LL1. |
| 22 | VBST1 | power_in | Supply input for the channel-1 high-side N-channel MOSFET driver (bootstrap/boost terminal). Referenced to LL1, range -0.1 V to 5.5 V with respect to LL1. |
| 23 | PGOOD | output | Power Good window comparator output for channels 1 and 2 (logical AND). Open-drain style status output. |
| 24 | VO1 | bidirectional | Output connection to SMPS channel 1. Works as a fixed voltage input and output discharge input, and as the 5-V switch-over return power input. |
| 25 | PowerPAD | power_in | Exposed thermal pad on package underside. Connect to the ground plane for thermal dissipation and electrical ground. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | QFN-24-EP(4x4) |
| Category | PMIC |
| Pins | 25 |
Ordering variants
Same part, different packaging or reel option.
TPS51125RGERTPS51125RGERRGET
CAD (KiCad official)
- Symbol:
TPS51125RGER - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm - 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (37 pp, sha256
06b57875a75f4b97, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).