component
TPS51123RGER
Public Unreviewedby Ray
Texas Instruments AC-DC Controllers and Regulators, VQFN-24-EP(4x4). Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads when scrolled away or the tab is hidden.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads when scrolled away or the tab is hidden.
PCB Footprint
Open full view ↗Loads on click. Unloads when scrolled away or the tab is hidden.
Datasheet
Open in new tab ↗Loads on click. Unloads when scrolled away or the tab is hidden.
README
markdownTPS51123RGER
Texas Instruments · AC-DC Controllers and Regulators · VQFN-24-EP(4x4)
TPS51123RGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | TRIP1 | bidirectional | Channel 1 OCL trip setting pin. Connect a resistor from this pin to GND to set the overcurrent threshold for the synchronous RDS(on) current sense (ITRIP typ 10 μA, 4500 ppm/°C). |
| 2 | VFB1 | input | Channel 1 SMPS feedback input. Connect to the output via a feedback resistor divider; regulates to the 2-V internal reference. |
| 3 | VREF | output | 2-V (±1%) internal reference voltage output. Bypass with a 220-nF to 1-μF ceramic capacitor to signal GND close to the device. |
| 4 | TONSEL | input | On-time / switching-frequency selection pin. Tie to VREG5 (365/460 kHz), VREG3 (300/375 kHz), VREF (245/305 kHz), or GND (200/250 kHz). |
| 5 | VFB2 | input | Channel 2 SMPS feedback input. Connect to the output via a feedback resistor divider; regulates to the 2-V internal reference. |
| 6 | TRIP2 | bidirectional | Channel 2 OCL trip setting pin. Connect a resistor from this pin to GND to set the overcurrent threshold for the synchronous RDS(on) current sense. |
| 7 | VO2 | bidirectional | Channel 2 output-voltage connection to the SMPS. Acts as a fixed voltage input and output-discharge sink, and also as the 3.3-V switch-over return power input for the VREG3 LDO. |
| 8 | VREG3 | power_out | 3.3-V, 100-mA internal LDO output. Bypass with a 1-μF (unloaded) or 10-μF ceramic capacitor to power GND near the device. |
| 9 | VBST2 | power_in | Channel 2 high-side N-channel MOSFET driver bootstrap supply. Connect a bootstrap capacitor (typ 0.1 μF) between VBST2 and LL2; internal boot diode charges from VREG5. |
| 10 | DRVH2 | output | Channel 2 high-side N-channel MOSFET gate driver output. Referenced to LL2. Rsource ≈ 4 Ω, Rsink ≈ 1.5 Ω. |
| 11 | LL2 | input | Channel 2 switch-node sense input. Provides high-side driver return, current-limit sensing, and control-loop timing reference. |
| 12 | DRVL2 | output | Channel 2 low-side N-channel MOSFET gate driver output. Referenced to GND, supplied from VREG5. Rsource ≈ 4 Ω, Rsink ≈ 1.5 Ω. |
| 13 | EN0 | bidirectional | Master enable input. Open (2.4-V enable threshold) turns the LDOs on and readies both switcher channels; tie to GND to disable the entire device. |
| 14 | SKIPSEL | input | Operation-mode select pin. Tie to VREG3/VREG5 for OOA auto-skip, to VREF for PWM-only, or to GND for standard auto-skip light-load operation. |
| 15 | GND | power_in | Device ground. The QFN PowerPAD on the underside should also be soldered to the GND plane with 3×3 thermal vias for the specified 1.85 W dissipation rating. |
| 16 | VIN | power_in | High-voltage power supply input for the 5-V and 3.3-V LDOs. Recommended operating range 5.5 V to 28 V (abs max 30 V). |
| 17 | VREG5 | power_out | 5-V, 100-mA internal LDO output; also supplies the low-side gate drivers and boot-diode source. Bypass with a 33-μF ceramic capacitor to power GND near the device. |
| 18 | ENC | input | Channel 1 and Channel 2 SMPS enable input. Pull up to 3.3-5 V to enable both switcher channels; short to GND to shut both channels down (enable threshold 2 V, shutdown ≤ 0.6 V). |
| 19 | DRVL1 | output | Channel 1 low-side N-channel MOSFET gate driver output. Referenced to GND, supplied from VREG5. Rsource ≈ 4 Ω, Rsink ≈ 1.5 Ω. |
| 20 | LL1 | input | Channel 1 switch-node sense input. Provides high-side driver return, current-limit sensing, and control-loop timing reference. |
| 21 | DRVH1 | output | Channel 1 high-side N-channel MOSFET gate driver output. Referenced to LL1. Rsource ≈ 4 Ω, Rsink ≈ 1.5 Ω. |
| 22 | VBST1 | power_in | Channel 1 high-side N-channel MOSFET driver bootstrap supply. Connect a bootstrap capacitor (typ 0.1 μF) between VBST1 and LL1; internal boot diode charges from VREG5. |
| 23 | PGOOD | output | Combined power-good open-drain output (logical AND of channel 1 and channel 2 power-good). Sink capability 5 mA min at 0.5 V; pull up externally. |
| 24 | VO1 | bidirectional | Channel 1 output-voltage connection to the SMPS. Acts as a fixed voltage input and output-discharge sink, and also as the 5-V switch-over return power input for the VREG5 LDO. |
| PAD | PowerPAD | power_in | Exposed thermal pad on the underside of the QFN. Must be soldered to the GND plane (recommended 3×3 thermal via array) for the rated 1.85 W dissipation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-24-EP(4x4) |
| Category | PMIC |
| Pins | 25 |
Ordering variants
Same part, different packaging or reel option.
TPS51123RGERTPS51123RGERRGET
CAD (KiCad official)
- Symbol:
TPS51123RGER - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm - 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (38 pp, sha256
c26be1d356b1d431, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).