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README

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TPS25940ARVCR

Texas Instruments · Monitors & Reset Circuits · WQFN-20-EP(3x4)

TPS25940ARVCR from Texas Instruments, in a WQFN-20-EP(3x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DEVSLP input Active-high DevSleep mode control input. A logic high (threshold ~1.85 V rising) activates the DevSleep low-power mode. Input leakage ~1 uA over 0.2 V to 18 V range.
2 PGOOD output Power-good open-drain output. Asserts high (via external pull-up) when PGTH input has crossed its threshold, indicating output voltage is valid. Sink current up to 10 mA.
3 PGTH input Positive (sense) input of the internal PGOOD comparator. A resistor divider from OUT to GND sets the PGOOD assertion threshold.
4 OUT power_out Power output of the device (drain-side of internal FET). Pins 4-8 are tied together internally to carry the pass-FET current. Requires >=0.1 uF external capacitor.
5 OUT power_out Power output of the device (drain-side of internal FET). Pins 4-8 are tied together internally to carry the pass-FET current.
6 OUT power_out Power output of the device (drain-side of internal FET). Pins 4-8 are tied together internally to carry the pass-FET current.
7 OUT power_out Power output of the device (drain-side of internal FET). Pins 4-8 are tied together internally to carry the pass-FET current.
8 OUT power_out Power output of the device (drain-side of internal FET). Pins 4-8 are tied together internally to carry the pass-FET current.
9 IN power_in Power input and supply voltage of the device (source-side of internal FET). Pins 9-13 are tied together internally. Operating range 2.7 V to 18 V (20 V abs max, 22 V transient).
10 IN power_in Power input and supply voltage of the device. Pins 9-13 are tied together internally.
11 IN power_in Power input and supply voltage of the device. Pins 9-13 are tied together internally.
12 IN power_in Power input and supply voltage of the device. Pins 9-13 are tied together internally.
13 IN power_in Power input and supply voltage of the device. Pins 9-13 are tied together internally.
14 EN/UVLO input Enable and programmable undervoltage lockout input (threshold ~0.99 V rising, ~0.92 V falling). An undervoltage event opens the internal FET and asserts FLT to indicate power-failure. When pulled to GND, resets the fault latch on the TPS25940L.
15 OVP input Programmable overvoltage protection threshold input (threshold ~0.99 V rising, ~0.92 V falling). An overvoltage event opens the internal FET and asserts FLT to indicate overvoltage.
16 GND power_in Device ground return. Must be connected to the exposed thermal PowerPAD.
17 ILIM bidirectional Current-limit programming pin. A resistor from ILIM to GND (16.9 kOhm to 150 kOhm) sets the overload and short-circuit current limit (~0.58 A at 150 kOhm to ~5.2 A at 16.9 kOhm). ILIM bias voltage ~0.87 V.
18 dVdT bidirectional Output ramp control. A capacitor from dVdT to GND sets the ramp rate (dV/dt) of the output voltage. Internal ~1 uA charging source; gain of dVdT-to-OUT ~11.9 V/V; V(dVdTmax) ~2.88 V.
19 IMON output Analog current monitor output. Sources a scaled-down replica of the internal FET current; a resistor from IMON to GND converts current to a proportional voltage. Recommended R(IMON) ~1 kOhm range; V(IMON) up to 6 V.
20 FLT output Active-low fault-event indicator (open-drain). Goes low to indicate a fault condition due to undervoltage, overvoltage, reverse voltage, or thermal shutdown. Sink current up to 10 mA.
PAD PowerPAD power_in Exposed thermal pad. Must be tied to the GND pin (pin 16) and connected to a PCB ground plane using multiple vias for good thermal performance.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-20-EP(3x4)
Category Power Supply Chip
Pins 21

Ordering variants

Same part, different packaging or reel option.

  • TPS25940ARVCR
  • TPS25940ARVCRRVCT

CAD (KiCad official)

  • Symbol: TPS25940ARVCR
  • Footprint: Package_DFN_QFN:QFN-20-1EP_3x4mm_P0.5mm_EP1.65x2.65mm
  • 3D model: WQFN-20-EP(3x4) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (46 pp, sha256 460f53fd0c00c9b7, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF