component

TMI7604R

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by Ray

TMI Power Over Ethernet (PoE) Controllers, QFN-48(7x7). Datasheet-verified pinout, KiCad symbol/footprint/3D.

componentpower management (pmic)tmi7604r
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Datasheet

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Contents

README

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TMI7604R

TMI · Power Over Ethernet (PoE) Controllers · QFN-48(7x7)

TMI7604R from TMI, in a QFN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No internal connection.
2 IC0 passive Internally connected. Not connected or connect to AGND.
3 PortN0 power_in Port 0 negative feeding voltage input. Connects to the RJ45 return leg through the transformer center tap for PoE port 0.
4 IC1 passive Internally connected. Not connected or connect to AGND.
5 PortN1 power_in Port 1 negative feeding voltage input. PoE port 1 return.
6 AGND power_in Analog ground.
7 IC2 passive Internally connected. Not connected or connect to AGND.
8 PortN2 power_in Port 2 negative feeding voltage input. PoE port 2 return.
9 IC3 passive Internally connected. Not connected or connect to AGND.
10 PortN3 power_in Port 3 negative feeding voltage input. PoE port 3 return.
11 NC unconnected No internal connection.
12 SCAN_MODE input Test scan mode input. Internally pulled down to AGND. Should be tied to AGND for normal operation.
13 ALT_A/B input ALT_A/B type select. Latched at power-on reset. Internally pulled down to DGND. 0 = ALT_A (default), 1 = ALT_B.
14 EN_CL4+ input Class4+ enable input, referenced to DGND, internally pulled down. Leave open for IEEE 802.3at mode; tie to V3P3 to enable Class4+ detection/classification. Latched at power-up / reset.
15 PMAX input Maximum-loading power setting pin. Connect a 75kΩ resistor to AGND to set total 4-port power budget (Pmax = Rmax * 39uA * V54). Latched during IC power-up / reset.
16 RGND power_in Low-noise analog reference ground. Connect to AGND.
17 V54 power_in Main power supply input for the chip (44-57V). Bypass with a 1µF capacitor between V54 and AGND.
18 AGND power_in Analog ground.
19 AUTO input Auto/shutdown mode input, referenced to AGND. Internally pulled up to V3P3 (leave open for auto mode). Tie to DGND for default shutdown. Also selects EEPROM vs I2C mode of the SCL/SDAI pair. Latched after power-up or reset.
20 V3P3 power_out 3.3V rail. Internal LDO output (up to 6mA external) when EnB_Reg=AGND, or external 3.3V input (≥3mA) when EnB_Reg=3.3V. Bypass with a 4.7µF capacitor to AGND.
21 2-EVENT input 2-Event classification select, referenced to AGND. Internally pulled up. Leave open to enable 2-Event classification; drive low to disable.
22 IC4 passive Internally connected. Leave unconnected.
23 NC unconnected No internal connection.
24 EnB_Reg input Enable/disable internal 3.3V regulator. Internally pulled up to V3P3. Tie low to enable the internal LDO; leave high (or drive to V3P3) to use an external 3.3V supply on V3P3.
25 NC unconnected No internal connection.
26 NC unconnected No internal connection.
27 NC unconnected No internal connection.
28 NC unconnected No internal connection.
29 NC unconnected No internal connection.
30 NC unconnected No internal connection.
31 NC unconnected No internal connection.
32 NC unconnected No internal connection.
33 NC unconnected No internal connection.
34 NC unconnected No internal connection.
35 NC unconnected No internal connection.
36 NC unconnected No internal connection.
37 LED_CLK output Serial LED clock output for the built-in multi-port LED controller.
38 LED_DAT output Serial LED data output for the built-in multi-port LED controller.
39 SCL/EE_CLK bidirectional AUTO=0: I2C host clock input. AUTO=1: clock output to external EEPROM.
40 SDAO output I2C serial data output (open-drain SDA return leg from the slave interface).
41 SDAI/EE_DAT bidirectional AUTO=0: I2C serial data input. AUTO=1: data input from external EEPROM.
42 INTB output Interrupt output, active low. Open-drain style alert to the management host.
43 DGND power_in Digital ground. Connect to AGND.
44 DV3P3 power_in Digital 3.3V supply. Internally connected to V3P3; external connections are usually also tied to V3P3.
45 RstN input Active-low reset input for TMI7604R.
46 AD2 input I2C device address bit AD2 (used to place up to 8 TMI7604R devices on the same I2C bus).
47 AD1 input I2C device address bit AD1.
48 AD0 input I2C device address bit AD0.
49 EPAD power_in Exposed thermal pad on package underside. Connect to AGND for both ground return and thermal dissipation.

Key specifications

Parameter Value
Manufacturer TMI
Package QFN-48(7x7)
Category Power Management (PMIC)
Pins 49

Ordering variants

Same part, different packaging or reel option.

  • TMI7604R

CAD (KiCad official)

  • Symbol: TMI7604R
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: QFN-48(7x7) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TMI datasheet (29 pp, sha256 892603f932729e9f, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF