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TMC5160A-TA-T

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by Ray

TRINAMIC Motion Control GmbH Stepper Motor Driver, TQFP-48-EP(7x7). Datasheet-verified pinout, KiCad symbol/footprint/3D.

componentmotor driver icstmc5160a-ta-t
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Contents

README

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TMC5160A-TA-T

TRINAMIC Motion Control GmbH · Stepper Motor Driver · TQFP-48-EP(7x7)

TMC5160A-TA-T from TRINAMIC Motion Control GmbH, in a TQFP-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 HB1 output High-side gate driver output for coil B, bridge 1 (drives external high-side MOSFET gate).
2 CB1 passive Bootstrap capacitor positive connection for the coil B / bridge 1 high-side driver.
3 12VOUT power_out Output of internal 11.5V gate-voltage regulator and supply pin for the low-side gate drivers. Attach 2.2-10 µF ceramic capacitor to GND. Tie to VSA when using an external gate supply.
4 VSA power_in Analog supply voltage for the 11.5V and 5V regulators. Normally tied to VS with a 100 nF filter capacitor.
5 5VOUT power_out Output of the internal 5V regulator. Attach 2.2-10 µF ceramic capacitor to GNDA. Used as the source for the chip's VCC supply.
6 GNDA power_in Analog ground. Connect to GND plane near the pin.
7 SRAL input Sense-resistor GND-side (Kelvin) connection for phase A. Compensates voltage drop on the GND interconnect.
8 SRAH input Sense-resistor high-side connection for phase A (Kelvin). Symmetrical RC filtering on SRAL/SRAH is recommended in noisy systems.
9 SRBH input Sense-resistor high-side connection for phase B (Kelvin). Symmetrical RC filtering on SRBL/SRBH is recommended in noisy systems.
10 SRBL input Sense-resistor GND-side (Kelvin) connection for phase B. Compensates voltage drop on the GND interconnect.
11 TST_MODE input Test mode input. Tie to GND using a short wire in normal operation.
12 CLK input Clock input. Tie to GND with a short wire to use the internal oscillator, or supply a 12-16 MHz external clock. Internal clock-fail circuitry protects against loss of the external clock.
13 CSN_CFG3 input SPI chip select (active low) when SPI_MODE=1; standalone configuration input CFG3 when SPI_MODE=0.
14 SCK_CFG2 input SPI serial clock when SPI_MODE=1; standalone configuration input CFG2 when SPI_MODE=0.
15 SDI_CFG1 input SPI data input when SPI_MODE=1; standalone configuration input CFG1 when SPI_MODE=0; also used as next-address input (NAI) for the single-wire UART chained interface.
16 SDO_CFG0 tri_state SPI data output (tristate) when SPI_MODE=1; standalone configuration input CFG0 when SPI_MODE=0; also used as next-address output (NAO) for the single-wire UART chained interface.
17 REFL_STEP input Left reference switch input for the internal ramp generator (SD_MODE=0), or STEP input in Step/Dir mode (SD_MODE=1).
18 REFR_DIR input Right reference switch input for the internal ramp generator (SD_MODE=0), or DIR input in Step/Dir mode (SD_MODE=1).
19 GNDD power_in Digital ground. Connect to GND plane near the pin.
20 VCC_IO power_in 3.3V to 5V I/O supply voltage for all digital pins.
21 SD_MODE input Mode select: low = internal ramp generator produces step pulses; high = external STEP/DIR inputs control the driver. SD_MODE=0 with SPI_MODE=0 enables UART operation.
22 SPI_MODE input Mode select: low with SD_MODE=1 places the chip in standalone mode (pins use CFG functions); high enables the SPI interface. Internal pull-down.
23 ENCB_DCEN_CFG4 input Encoder B-channel input (internal ramp mode), DcStep enable input (Step/Dir + SPI mode), or standalone configuration input CFG4. Internal pull-down.
24 ENCA_DCIN_CFG5 input Encoder A-channel input (internal ramp mode), DcStep gating input for axis synchronization (Step/Dir + SPI mode), or standalone configuration input CFG5. Internal pull-down.
25 ENCN_DCO_CFG6 bidirectional Encoder N-channel input (SD_MODE=0) or DcStep ready output (SD_MODE=1). If unused, tie to GND or VCC_IO.
26 DIAG0_SWN bidirectional Diagnostics output DIAG0 (interrupt or STEP output) with SD_MODE=0/SPI_MODE=1; also serves as single-wire UART I/O (negative) when SD_MODE=0 and SPI_MODE=0. Open-drain - use external pull-up (<=47 k).
27 DIAG1_SWP bidirectional Diagnostics output DIAG1 (position-compare or DIR output) with SD_MODE=0/SPI_MODE=1; also serves as single-wire UART I/O (positive) when SD_MODE=0 and SPI_MODE=0. Open-drain - use external pull-up (<=47 k).
28 DRV_ENN input Driver enable input (active low). When driven high, the power stage is switched off and all motor outputs float.
29 VCC power_in 5V supply input for the chip's digital circuitry. Provide 100 nF decoupling to GND. Typically supplied from 5VOUT through a 2.2-3.3 Ω decoupling resistor. Must come up before or with 5VOUT/VCC_IO.
30 GNDD power_in Digital ground. Connect to GND plane near the pin.
31 CPO passive Charge-pump capacitor output. Connect a 22 nF / 100 V capacitor between CPO and CPI.
32 CPI passive Charge-pump capacitor input. Tie to CPO through the 22 nF / 100 V charge-pump capacitor.
33 VS power_in Motor supply voltage input. Provide bulk filtering near the pin with a short loop to GND; must be tied to the positive bridge supply voltage (8-60 V DC).
34 VCP passive Charge-pump voltage. Tie to VS through a 100 nF capacitor to buffer the charge-pump output.
35 CA2 passive Bootstrap capacitor positive connection for the coil A / bridge 2 high-side driver.
36 HA2 output High-side gate driver output for coil A, bridge 2 (drives external high-side MOSFET gate).
37 BMA2 passive Bridge-center node for coil A, bridge 2, and bootstrap capacitor negative reference for the HA2 high-side driver.
38 LA2 output Low-side gate driver output for coil A, bridge 2 (drives external low-side MOSFET gate).
39 LA1 output Low-side gate driver output for coil A, bridge 1 (drives external low-side MOSFET gate).
40 BMA1 passive Bridge-center node for coil A, bridge 1, and bootstrap capacitor negative reference for the HA1 high-side driver.
41 HA1 output High-side gate driver output for coil A, bridge 1 (drives external high-side MOSFET gate).
42 CA1 passive Bootstrap capacitor positive connection for the coil A / bridge 1 high-side driver.
43 CB2 passive Bootstrap capacitor positive connection for the coil B / bridge 2 high-side driver.
44 HB2 output High-side gate driver output for coil B, bridge 2 (drives external high-side MOSFET gate).
45 BMB2 passive Bridge-center node for coil B, bridge 2, and bootstrap capacitor negative reference for the HB2 high-side driver.
46 LB2 output Low-side gate driver output for coil B, bridge 2 (drives external low-side MOSFET gate).
47 LB1 output Low-side gate driver output for coil B, bridge 1 (drives external low-side MOSFET gate).
48 BMB1 passive Bridge-center node for coil B, bridge 1, and bootstrap capacitor negative reference for the HB1 high-side driver.
EP GND_PAD power_in Exposed die pad (PAD = GNDD, GNDP). Connect to GND plane with many vias for heat transfer and as GND return for the low-side gate drivers; ensure a low-inductance loop to sense-resistor GND.

Key specifications

Parameter Value
Manufacturer TRINAMIC Motion Control GmbH
Package TQFP-48-EP(7x7)
Category Motor Driver ICs
Pins 49

Ordering variants

Same part, different packaging or reel option.

  • TMC5160A-TA-T
  • TMC5160-TA
  • TMC5160-TA-T
  • TMC5160A-WA
  • TMC5160A-WA-T
  • TMC5160-WA
  • TMC5160-WA-T

CAD (KiCad official)

  • Symbol: TMC5160A-TA-T
  • Footprint: Package_QFP:TQFP-48-1EP_7x7mm_P0.5mm_EP5x5mm
  • 3D model: TQFP-48-EP(7x7) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TRINAMIC Motion Control GmbH datasheet (134 pp, sha256 3717e1e9efe5a9bc, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF