TLE9262QX from Infineon, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	GND	power_in	Device ground reference. Must be tied to a common GND potential with all other GND pins and the exposed cooling tab.
2	n.c.	unconnected	Not connected; internally not bonded. Recommended to tie to GND per unused-pin guidance.
3	VCC3REF	power_in	Voltage Regulator 3 reference input: collector connection for the external PNP pass transistor used by the tracker/external regulator VCC3.
4	VCC3B	output	Voltage Regulator 3 base drive: base connection for the external PNP pass transistor of VCC3.
5	VCC3SH	power_in	Voltage Regulator 3 sense: emitter connection for the external PNP and shunt-resistor connection used for current sensing / load sharing of VCC3.
6	n.c.	unconnected	Not connected; internally not bonded. Tie to GND if convenient.
7	n.c.	unconnected	Not connected; internally not bonded. Tie to GND if convenient.
8	HS1	output	High-Side Output 1 supplied from VSHS. Typical RDS(on) ~7 Ω. Used to drive external loads (LEDs, relays) with PWM/timer support.
9	HS2	output	High-Side Output 2 supplied from VSHS. Typical RDS(on) ~7 Ω.
10	HS3	output	High-Side Output 3 supplied from VSHS. Typical RDS(on) ~7 Ω.
11	HS4	output	High-Side Output 4 supplied from VSHS. Typical RDS(on) ~7 Ω.
12	n.c.	unconnected	Not connected; internally not bonded.
13	VSHS	power_in	Supply voltage for high-side switches, LIN transceiver and GPIO1/2 in HS configuration, with its own UV/OV supervision. Connect to battery through a reverse-protection diode and EMC filter; tie to VS if a separate supply is not required. Absolute max 28 V (40 V load dump).
14	VS	power_in	Chip main supply for internal circuitry and voltage regulators. Connect to battery through a reverse-protection diode and EMC filter. Absolute max 28 V (40 V load dump).
15	VS	power_in	Second VS pin bonded to the same internal supply as pin 14; both VS pins must be connected together to battery potential through the reverse-protection diode and EMC filter.
16	n.c.	unconnected	Not connected; internally not bonded.
17	VCC1	power_out	Voltage Regulator 1 output (main 5 V rail for the microcontroller and internal logic reference). Requires an external bypass/decoupling capacitor to GND.
18	VCC2	power_out	Voltage Regulator 2 output (protected tracker output for peripheral supply, e.g. sensors). Leave open and disable via SPI if unused.
19	n.c.	unconnected	Not connected; internally not bonded.
20	GND	power_in	Ground reference; tie to the common GND plane with all other GND pins and the exposed cooling tab.
21	FO1	output	Fail Output 1 (open-drain, active low). Used to signal safety-related SBC failures to the system.
22	WK1	input	Wake Input 1: high-voltage wake / voltage-monitoring input, tolerant to battery voltage. Alternate function: HV-measurement source pin when paired with WK2 (see Chapter 12.2.2).
23	WK2	input	Wake Input 2: high-voltage wake / voltage-monitoring input. Alternate function: HV-measurement output pin when paired with WK1.
24	WK3	input	Wake Input 3: high-voltage wake input tolerant to battery voltage, usable in cyclic-sense/wake schemes.
25	N.U.	unconnected	Not Used; reserved for internal test. Do not connect on the board (leave open, or provide an open-bridge jumper).
26	N.U.	unconnected	Not Used; reserved for internal test. Do not connect on the board (leave open, or provide an open-bridge jumper).
27	CLK	input	SPI clock input from the microcontroller (SCK). Logic levels referenced to VCC1.
28	SDI	input	SPI serial data input into the SBC (MOSI).
29	SDO	output	SPI serial data output from the SBC (MISO). Tri-stated when CSN is high.
30	CSN	input	SPI chip-select (active low). Frames the SPI transaction to the SBC.
31	INT	output	Interrupt output (active low) used as wake-up flag in SBC Stop/Normal mode and for indicating failures. Doubles as SBC configuration select at start-up: external pull-up selects config 1/3, no external pull-up selects config 2/4.
32	RO	output	Reset output to the microcontroller (active low). Open-drain style output requiring external pull-up.
33	TXDLIN1	input	LIN1 transmit-data input from the microcontroller (logic-level LIN TX).
34	RXDLIN1	output	LIN1 receive-data output to the microcontroller (logic-level LIN RX).
35	TXDCAN	input	HS-CAN transmit-data input from the microcontroller (CAN TXD).
36	RXDCAN	output	HS-CAN receive-data output to the microcontroller (CAN RXD).
37	VCAN	power_in	Supply input for the internal HS-CAN transceiver cell (5 V). Typically connected to VCC1; absolute max 5.5 V.
38	GND	power_in	Ground reference for the CAN transceiver; tie to the common GND plane.
39	CANL	bidirectional	HS-CAN low bus line, per ISO 11898-2/-5. Connect to the CAN bus through the standard termination network.
40	CANH	bidirectional	HS-CAN high bus line, per ISO 11898-2/-5. Supports CAN FD.
41	n.c.	unconnected	Not connected; internally not bonded.
42	LIN1	bidirectional	LIN1 bus line, compliant with ISO 9141 and LIN 2.2 as well as SAE J2602-2. Supplied from VSHS.
43	GND	power_in	Ground reference; tie to the common GND plane.
44	N.U.	unconnected	Not Used; internal test purpose. Do not connect on the board (leave open, or provide an open-bridge jumper).
45	n.c.	unconnected	Not connected; internally not bonded.
46	n.c.	unconnected	Not connected; internally not bonded.
47	FO2	output	Fail Output 2 / Side-indicator driver: 1.25 Hz 50% duty-cycle output, open drain, active low. Alternate function: GPIO1 configurable as WK, LS, or HS (VSHS-supplied) via SPI (GPIO_CTRL).
48	FO3/TEST	bidirectional	Fail Output 3 / Pulsed-light output (brake/rear light, 100 Hz 20% duty, open drain, active low). Also TEST pin: pull to GND at power-up to enter SBC Software Development Mode (internal pull-up, so tie to VS via pull-up or leave open for normal operation). Alternate function: GPIO2 configurable as WK, LS, or HS (VSHS-supplied) via SPI.
EP	GND	power_in	Exposed cooling tab (die pad) on package bottom. Provided for heat dissipation; recommended to be tied to GND for best EMC performance (must not be used as a signal ground path).

Key specifications

Parameter	Value
Manufacturer	Infineon
Package	VQFN-48-EP(7x7)
Category	Interface
Pins	49

Ordering variants

Same part, different packaging or reel option.

TLE9262QX

CAD (KiCad official)

Symbol: TLE9262QX
Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Infineon datasheet (163 pp, sha256 42db88594a226a58, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF