component
tlc271aidr
Public Unreviewedby Ray
Texas Instruments Operational Amplifier, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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README
markdownTLC271AIDR
Texas Instruments · Operational Amplifier · SOIC-8
TLC271AIDR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OFFSET N1 | passive | Offset-null terminal 1. Connect an external trim potentiometer between OFFSET N1 (pin 1) and OFFSET N2 (pin 8) with the wiper returned to VDD to null the input offset voltage. Leave open if trim is not used. |
| 2 | IN- | input | Inverting analog input of the op-amp. High-impedance CMOS gate input (~10^12 Ω); common-mode range extends below the negative rail on C/I-suffix parts. Input voltage must remain within -0.3 V to VDD absolute-max limits. |
| 3 | IN+ | input | Non-inverting analog input of the op-amp. High-impedance CMOS gate input (~10^12 Ω); common-mode range extends below the negative rail on C/I-suffix parts. Input current is limited to ±5 mA absolute max. |
| 4 | GND | power_in | Negative supply / ground reference (V-). In single-supply operation tie to 0 V; in split-supply operation tie to the negative rail. Supply voltage between VDD and GND is 3-16 V (0 °C to 70 °C range). |
| 5 | BIAS SELECT | input | Bias-mode programming pin. Tie to GND for high-bias (fast/highest quiescent current, ~3.4 mW at 5 V), tie between 1 V and VDD-1 V (typically the supply midpoint) for medium-bias (~0.5 mW), or tie to VDD for low-bias (~0.05 mW). Sets slew rate, gain-bandwidth, noise, and power dissipation. |
| 6 | OUT | output | Op-amp output. Rail-to-negative-rail output swing (output includes the negative rail). Short-circuit current is limited internally; ±30 mA absolute maximum output current. |
| 7 | VDD | power_in | Positive supply rail (V+). Operating range 3-16 V (0 °C to 70 °C), 4-16 V (-40 °C to 85 °C), 5-16 V (-55 °C to 125 °C); 18 V absolute maximum. Bypass locally with a ceramic capacitor to GND. |
| 8 | OFFSET N2 | passive | Offset-null terminal 2. Used with OFFSET N1 (pin 1) and an external potentiometer whose wiper is returned to VDD to trim input offset voltage. Leave open if trim is not used. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Op-amp/Cmp |
| Pins | 8 |
Ordering variants
TLC271AIDRTLC271AIDRBIDTLC271AIDRBIDRTLC271AIDRCDTLC271AIDRCDRTLC271AIDRBCDTLC271AIDRBCDRTLC271AIDRACDTLC271AIDRACDRTLC271AIDRIPTLC271AIDRBIPTLC271AIDRAIPTLC271AIDRCPTLC271AIDRBCPTLC271AIDRACPTLC271AIDRMPTLC271AIDRMJGTLC271AIDRMFK
CAD (KiCad official)
- Symbol:
TLC271AIDR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (None pp, sha256
462161034a481a4b, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).
Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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