component

TL071CDT

Public Unreviewed

by Ray

STMicroelectronics FET InputAmplifiers, SO-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.

componentop-amp-cmptl071cdt
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3D Model

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Symbol & Footprint

Schematic Symbol

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PCB Footprint

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Datasheet

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Contents

README

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TL071CDT

STMicroelectronics · FET InputAmplifiers · SO-8

TL071CDT from STMicroelectronics, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OFFSET_N1 passive Offset null 1. Connect an external 100 kΩ potentiometer between OFFSET_N1 (pin 1) and OFFSET_N2 (pin 5) with the wiper tied to VCC- to trim input offset voltage.
2 IN- input Inverting input of the op-amp. High-impedance JFET gate input (typ input resistance ~10^12 Ω, input bias current 20 pA typ). Input voltage range ±15 V max.
3 IN+ input Non-inverting input of the op-amp. High-impedance JFET gate input (typ input resistance ~10^12 Ω, input bias current 20 pA typ). Common-mode input range typ +15/-12 V.
4 VCC- power_in Negative supply rail. Dual-supply range ±18 V max (single-supply 6 to 36 V). Typical quiescent supply current 1.4 mA.
5 OFFSET_N2 passive Offset null 2. Paired with OFFSET_N1 (pin 1) for input offset voltage trimming via an external 100 kΩ potentiometer whose wiper connects to VCC-.
6 OUT output Op-amp output. Short-circuit protected (typ short-circuit current 40 mA). Output voltage swing typ ±12 V with RL=2 kΩ, slew rate 16 V/µs typ.
7 VCC+ power_in Positive supply rail. Dual-supply range ±18 V max (single-supply 6 to 36 V). Typical quiescent supply current 1.4 mA.
8 NC unconnected No internal connection. Leave floating or tie to a convenient net; do not use to route signals.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package SO-8
Category Op-amp/Cmp
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • TL071CDTD
  • TL071CDT
  • TL071CDTN

CAD (KiCad official)

  • Symbol: TL071CDT
  • Footprint: Package_SO:TI_SO-PowerPAD-8
  • 3D model: SO-8 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
tl071cdt.step 123 KB You want the bare part, or you mark your own boards.
tl071cdt-etched.step 1.3 MB You want the part with TL071CDT already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 352 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (15 pp, sha256 7d84e188315bc01e, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF