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TL062CDR
Public Made by Adomby adom
Texas Instruments FET InputAmplifiers, SOIC-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownTL062CDR
Texas Instruments · FET InputAmplifiers · SOIC-8
TL062CDR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1OUT | output | Amplifier 1 output. Class-AB output stage with short-circuit protection; can drive loads to within a few volts of the supply rails. |
| 2 | 1IN- | input | Amplifier 1 inverting (negative) input. High-impedance JFET input; input bias current typically in the pA range. |
| 3 | 1IN+ | input | Amplifier 1 non-inverting (positive) input. High-impedance JFET input; common-mode range includes VCC+. |
| 4 | VCC- | power_in | Negative supply rail. Recommended operating range -5 V to -15 V (absolute max -18 V). Tied to GND for single-supply operation. |
| 5 | 2IN+ | input | Amplifier 2 non-inverting (positive) input. High-impedance JFET input; common-mode range includes VCC+. |
| 6 | 2IN- | input | Amplifier 2 inverting (negative) input. High-impedance JFET input; input bias current typically in the pA range. |
| 7 | 2OUT | output | Amplifier 2 output. Class-AB output stage with short-circuit protection; can drive loads to within a few volts of the supply rails. |
| 8 | VCC+ | power_in | Positive supply rail. Recommended operating range +5 V to +15 V (absolute max +18 V). Bypass with a 100 nF ceramic close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Op-amp/Cmp |
| Pins | 8 |
Ordering variants
Same part, different packaging or reel option.
TL062CDRDTL062CDRTL062CDRPTL062CDRJGTL062CDRPSTL062CDRPWTL062CDRFK
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VCC+ | VCC+ | 18 | V | Referenced to midpoint of VCC+ and VCC- | 4 | ||
| Supply voltage VCC- | VCC- | -18 | V | Referenced to midpoint of VCC+ and VCC- | 4 | ||
| Differential input voltage | VID | -30 | 30 | V | Printed as ±30 V; differential voltage at IN+ with respect to IN- | 4 | |
| Input voltage | VI | -15 | 15 | V | Printed as ±15 V; magnitude must not exceed supply magnitude or 15 V, whichever is less | 4 | |
| Operating virtual junction temperature | TJ | 150 | °C | 4 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Lead temperature (D, N, NS, P, PS or PW package) | 260 | °C | 1.6 mm (1/16 inch) from case for 10 seconds | 4 | |||
| Supply voltage VCC+ | VCC+ | 5 | 15 | V | 5 | ||
| Supply voltage VCC- | VCC- | -15 | -5 | V | Printed as –5 to –15 V; listed here in ascending order | 5 | |
| Ambient temperature (TL06xC) | TA | 0 | 70 | °C | TL06xC grade | 5 | |
| Input offset voltage | VIO | 3 | 15 | mV | TA = 25°C, VO = 0, RS = 50 Ω | 6 | |
| Input offset voltage | VIO | 20 | mV | TA = Full range, VO = 0, RS = 50 Ω | 6 | ||
| Input offset current | IIO | 5 | nA | TA = Full range, VO = 0 | 6 | ||
| Input bias current | IIB | 10 | nA | TA = Full range, VO = 0 | 6 | ||
| Common-mode input voltage range | VICR | -12 | 15 | V | TA = 25°C | 6 | |
| Maximum peak output voltage swing | VOM | -10 | 13.5 | V | RL = 10 kΩ, TA = 25°C | 6 | |
| Maximum peak output voltage swing | VOM | -10 | V | RL ≥ 10 kΩ, TA = Full range | 6 | ||
| Large-signal differential voltage amplification | AVD | 3 | 6 | V/mV | VO = ±10 V, RL ≥ 2 kΩ, TA = 25°C | 6 | |
| Large-signal differential voltage amplification | AVD | 3 | V/mV | VO = ±10 V, RL ≥ 2 kΩ, TA = Full range | 6 | ||
| Common-mode rejection ratio | CMRR | 70 | 86 | dB | VIC = VICRmin, VO = 0, RS = 50 Ω, TA = 25°C | 6 | |
| Supply-voltage rejection ratio | kSVR | 70 | 95 | dB | VCC = ±9 V to ±15 V, VO = 0, RS = 50 Ω, TA = 25°C | 6 | |
| Slew rate at unity gain | SR | 1.5 | 3.5 | V/μs | VI = 10 V, CL = 100 pF, RL = 10 kΩ, see Figure 16 | 8 | |
| Temperature coefficient of input offset voltage | αVIO | 10 | μV/°C | VO = 0, RS = 50 Ω, TA = Full range | 6 | ||
| Input offset current | IIO | 5 | 200 | pA | TA = 25°C, VO = 0 | 6 | |
| Input bias current | IIB | 30 | 400 | pA | TA = 25°C, VO = 0 | 6 | |
| Total power dissipation (each amplifier) | PD | 6 | 7.5 | mW | VO = 0, No load, TA = 25°C | 6 | |
| Supply current (each amplifier) | ICC | 200 | 250 | µA | VO = 0, No load, TA = 25°C | 6 | |
| Crosstalk attenuation | VO1/VO2 | 120 | dB | AVD = 100, TA = 25°C | 6 | ||
| Unity-gain bandwidth | B1 | 1 | MHz | RL = 10 kΩ, TA = 25°C | 6 | ||
| Rise time | tr | 0.2 | μs | VI = 20 V, CL = 100 pF, RL = 10 kΩ, see Figure 16 | 8 | ||
| Overshoot factor | 10 | % | VI = 20 V, CL = 100 pF, RL = 10 kΩ, see Figure 16 | 8 | |||
| Equivalent input noise voltage | Vn | 42 | nV/√Hz | RS = 20 Ω, f = 1 kHz | 8 | ||
| Junction-to-ambient thermal resistance (D, SOIC 8 pins) | RθJA | 97 | °C/W | D (SOIC) 8-pin package | 5 | ||
| ESD human body model (HBM) | V(ESD) | 2000 | V | HBM per ANSI/ESDA/JEDEC JS-001 | 5 | ||
| ESD charged-device model (CDM) | V(ESD) | 2000 | V | CDM per JEDEC JESD22-C101 | 5 |
CAD (KiCad official)
- Symbol:
TL062CDR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
tl062cdr-etched.step/tl062cdr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tl062cdr.step/tl062cdr.glbare the bare package body.
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
tl062cdr.step |
122 KB | You want the bare part, or you mark your own boards. |
tl062cdr-etched.step |
1.8 MB | You want the part with TL062CDR already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 440 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (52 pp, sha256
c5d08beb1f4c176d, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).