TC7SZ125F from TOSHIBA LJ CT, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	~G	input	Active-low output enable. When ~G is High the Y output is placed in the High-Impedance (Z) state; when ~G is Low the buffer drives Y with the logic level of input A. 5.5 V tolerant input.
2	A	input	Buffer data input. Its logic level (H/L) is passed to output Y when ~G is Low; input is 'don't care' when ~G is High. CMOS-level input, 5.5 V tolerant.
3	GND	power_in	Ground reference (0 V) for the device.
4	Y	tri_state	3-state buffer output. Drives the logic level of input A when ~G is Low; enters High-Impedance state when ~G is High. Guaranteed drive ±24 mA min at VCC = 3.0 V; output is 5.5 V power-down protected.
5	VCC	power_in	Positive supply input. Operating range 1.65 V to 5.5 V (data retention down to 1.5 V). Absolute maximum 6.0 V. Decouple with a 0.1 µF ceramic capacitor to GND close to the pin.

Key specifications

Parameter	Value
Manufacturer	TOSHIBA LJ CT
Package	SOT-23-5
Category	Logic
Pins	5

Ordering variants

Same part, different packaging or reel option.

TC7SZ125FFU

CAD (KiCad official)

Symbol: TC7SZ125F
Footprint: Package_TO_SOT_SMD:SOT-23-5
3D model: SOT-23-5 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: TOSHIBA LJ CT datasheet (9 pp, sha256 ae33bd61f241ae92, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF