TC7SH00FU from TOSHIBA LJ CT, in a SOT-353. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	IN B	input	Logic input B of the 2-input NAND gate. CMOS input, 5.5 V tolerant regardless of VCC. VIH = VCC x 0.7 (min), VIL = VCC x 0.3 (max) at VCC = 3.0-5.5 V. Input leakage +/-0.1 uA (typ).
2	IN A	input	Logic input A of the 2-input NAND gate. CMOS input, 5.5 V tolerant regardless of VCC. VIH = VCC x 0.7 (min), VIL = VCC x 0.3 (max) at VCC = 3.0-5.5 V. Unused inputs must be tied to VCC or GND.
3	GND	power_in	Ground reference (0 V) for the device.
4	OUT Y	output	NAND gate output Y = NOT(A AND B). CMOS push-pull output. VOH >= 4.4 V at VCC = 4.5 V (IOH = -50 uA); drives IOH = -8 mA / IOL = 8 mA at VCC = 4.5 V with VOH >= 3.94 V / VOL <= 0.36 V (typ., 25 C).
5	VCC	power_in	Positive supply voltage. Operating range VCC = 2.0 V to 5.5 V. Absolute max 7.0 V. Quiescent current ICC = 2.0 uA (max) at Ta = 25 C, VCC = 5.5 V.

Key specifications

Parameter	Value
Manufacturer	TOSHIBA LJ CT
Package	SOT-353
Category	Logic
Pins	5

Ordering variants

Same part, different packaging or reel option.

TC7SH00FU
TC7SH00FU(TE85L,F
TC7SH00FU(JCT

CAD (KiCad official)

Symbol: TC7SH00FU
Footprint: Package_TO_SOT_SMD:SOT-353_SC-70-5
3D model: SOT-353 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: TOSHIBA LJ CT datasheet (7 pp, sha256 29d1f03da6b4bc78, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF