SZ18201 from Motorcomm, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	RBIAS	passive	Bias resistor pin. An external 2.49 kΩ ±1% resistor must be connected between RBIAS and GND to set internal bias currents.
2	AVDDL_REG	power_out	Internal LDO analog power output rail. Decouple with a 1 µF and a 0.1 µF ceramic capacitor to GND.
3	TRXP0	bidirectional	Transmit/Receive positive of differential pair channel 0. Twisted-pair MDI line with 50 Ω internal termination; voltage-driven DAC, no center-tap supply required.
4	TRXN0	bidirectional	Transmit/Receive negative of differential pair channel 0. Twisted-pair MDI line with 50 Ω internal termination.
5	TRXP1	bidirectional	Transmit/Receive positive of differential pair channel 1. Twisted-pair MDI line with 50 Ω internal termination.
6	TRXN1	bidirectional	Transmit/Receive negative of differential pair channel 1. Twisted-pair MDI line with 50 Ω internal termination.
7	AVDD33	power_in	3.3 V analog power supply for the analog circuitry. Should be well decoupled.
8	RX_DV	output	Receive Data Valid (MII/RMII). Asserted while valid receive nibble data is present on RXD[3:0]; valid on rising edge of RXC. Internally weakly pulled low.
9	RXD[0]	output	Receive Data bit 0 of MII/RMII data bus. Internally weakly pulled low.
10	RXD[1]	output	Receive Data bit 1 of MII/RMII data bus. Internally weakly pulled low.
11	RXD[2]/INT_N	bidirectional	Receive Data bit 2 in MII mode; in RMII mode this pin is repurposed as the open-drain active-low interrupt output INT_N. Internally weakly pulled down.
12	RXD[3]/CLK_CTL	output	Receive Data bit 3 in MII mode; also latched at reset as the RMII CLK direction strap: 1 = REF_CLK input (RMII1), 0 = REF_CLK output (RMII2, default via internal weak pull-down).
13	RXC	output	Receive Clock for the MII bus. Continuous clock reference for RX_DV and RXD[3:0]: 25 MHz at 100 Mbps, 2.5 MHz at 10 Mbps.
14	DVDD33	power_in	3.3 V digital power supply input for digital circuitry.
15	TXC	bidirectional	MII Transmit Clock output (25 MHz at 100 Mbps, 2.5 MHz at 10 Mbps) reference for TXD[3:0] and TX_EN; in RMII mode acts as the synchronous 50 MHz reference clock (direction set by CLK_CTL strap; defaults to output when RXD[3]/CLK_CTL floats).
16	TXD[0]	input	Transmit Data bit 0 from the MAC. Internally weakly pulled down.
17	TXD[1]	input	Transmit Data bit 1 from the MAC. Internally weakly pulled down.
18	TXD[2]	input	Transmit Data bit 2 from the MAC. Internally weakly pulled down.
19	TXD[3]	input	Transmit Data bit 3 from the MAC. Internally weakly pulled down.
20	TX_EN	input	Transmit Enable (MII/RMII). Asserted by the MAC to indicate valid nibble data on TXD[3:0]. Internally weakly pulled down to prevent floating bus.
21	RESET_N	input	Active-low chip reset. High-impedance input (no internal pull); must be driven high for normal operation.
22	MDC	input	Management Data Clock, up to 2.5 MHz, provides the clock reference for MDIO. Internally weakly pulled up.
23	MDIO	bidirectional	Management Data Input/Output. Bi-directional serial data line of the MDIO management interface. Internally weakly pulled up.
24	LED0/PHYAD[0]	bidirectional	LED0 output (open-drain, active blink when 10 Mbps link is present) or PMEB Wake-on-LAN interrupt output, selected by the wol_led_sel strap on pin 10. Doubles as PHY address bit 0 sample-on-reset strap. Internally weakly pulled down.
25	LED1/PHYAD[1]	output	LED1 output (active blink when 100 Mbps link is present). Also sampled at reset as PHY address bit 1 (phy_address[1:0] selects addresses 00000-00011). Internally weakly pulled down.
26	CRS/CRS_DV	output	Carrier Sense in MII mode (asserted high when the medium is non-idle) or combined Carrier Sense/Receive Data Valid in RMII mode. Internally weakly pulled down.
27	COL	output	Collision Detect. Asserted high when a collision is detected on the medium. Internally weakly pulled down.
28	RX_ER	output	Receive Error output. Asserted synchronous to RXC when a coding error is detected in the received symbol stream. Internally weakly pulled down.
29	DVDDL_REG	power_out	Internal LDO digital power output rail. Decouple with a 1 µF and a 0.1 µF ceramic capacitor to GND.
30	NC	unconnected	No connect. Leave floating.
31	XTAL_IN	input	25 MHz crystal input, or single-ended input for an external 25 MHz clock/oscillator.
32	XTAL_OUT	output	25 MHz crystal output. Connect a 25 MHz crystal between XTAL_IN and XTAL_OUT with matched load capacitors to GND on each pin. Leave unconnected when driving XTAL_IN from an external oscillator.
33	EPAD	power_in	Exposed thermal pad on the back of the QFN package. Must be soldered and tied to the board ground for both electrical ground return and thermal dissipation.

Key specifications

Parameter	Value
Manufacturer	Motorcomm
Package	QFN-32-EP(5x5)
Category	Comm/UART
Pins	33

Ordering variants

Same part, different packaging or reel option.

SZ18201

CAD (KiCad official)

Symbol: SZ18201
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Motorcomm datasheet (76 pp, sha256 cbe0318c643d57f6, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF