Symbol & Footprint

Schematic Symbol

Open full view ↗

PCB Footprint

Open full view ↗
Contents

README

markdown

SY8745FCC

Silergy Corp · LED Drivers · SOIC-8-EP

SY8745FCC from Silergy Corp, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No connection. Leave floating or tie to a copper pour per layout guidance.
2 CF input Dimming filter / reference capacitor pin. In analog dimming mode, connect a ~10nF capacitor to filter the reference. Also used to select the dimming mode: when VCF>1.5V the IC operates in PWM dimming mode; when VCF<1.5V it operates in analog dimming mode. Also sets soft-start time via CCF.
3 LX output Switching node / inductor connection. Internal low-side power MOSFET switches this node to GND. Connect the external output inductor from the power input side to LX. Absolute maximum 63V; keep LX copper area small to reduce EMI/noise.
4 GND power_in Ground pin. Also tied to the exposed thermal pad on the SO8E package. Provide a large copper area / ground plane for thermal and noise performance (ΘJA=30°C/W, θJC=10°C/W).
5 IN power_in Input supply pin (10-60V operating, 63V absolute max). Decouple this pin to GND with a 1µF (or larger) X7R ceramic capacitor placed close to IN/GND. Also serves as the positive terminal of the internal current sense (VIN-VSEN).
6 SEN input Negative current sense input. Connects to the LED-side of the external current sense resistor RSEN (RSEN = 0.1V / ILED). Typical current sense limit 100mV (VIN-VSEN). Recommended operating range is VIN ± 0.4V (absolute max VIN ± 0.6V).
7 EN input Enable and PWM dimming input pin. EN rising threshold 1.0V, falling 0.5V. If VEN>8V the IC operates in 0~1V linear (analog) dimming mode with the dimming signal applied to CF. If VEN<8V the IC works in PWM/analog dimming on EN (add a ~10nF cap to CF). Absolute max 63V; IC shuts down ~10ms after EN goes low.
8 NC unconnected No connection. Leave floating or tie to a copper pour per layout guidance.
EP GND power_in Exposed thermal pad on the underside of the SO8E package, electrically tied to GND (pin 4). Solder to a large ground copper pour for thermal dissipation (PD=3.3W @ 25°C).

Key specifications

Parameter Value
Manufacturer Silergy Corp
Package SOIC-8-EP
Category LED-drv
Pins 9

Ordering variants

Same part, different packaging or reel option.

  • SY8745FCC

CAD (KiCad official)

  • Symbol: SY8745FCC
  • Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm
  • 3D model: SOIC-8-EP (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Silergy Corp datasheet (9 pp, sha256 99a9efb6f89adc4a, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF