SY8513FCC from Silergy Corp, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	IN	power_in	Input supply pin, 4.5V to 100V range (abs max 100V). Decouple to GND with at least a 1μF ceramic capacitor placed close to the pin.
2	EN	input	Enable control input. Pull high to turn on the converter (V_EN,R typ 1.1V rising, V_EN,F typ 0.9V falling). Do not leave floating. Abs max -0.3V to VIN+0.3V.
3	FS	input	Switching frequency programming pin. Connect a resistor from FS to GND to set fSW between 100kHz and 500kHz per fSW(kHz) = 1e5 / RFS(kΩ). RFS range 200kΩ to 1MΩ.
4	GND	power_in	Device ground reference. Tie to system ground plane; exposed pad must also be connected to this pin/ground.
5	FB	input	Output voltage feedback input to the error amplifier. Connect to the center tap of the output resistor divider to set VOUT = 0.8V × (1 + R1/R2). VREF = 0.8V ±1%; IFB ±50nA.
6	PG	output	Power-good indicator, open-drain output. Asserts (pulled low released to Hi-Z) when the FB voltage is within approximately 90% to 120% of the regulation point. Requires an external pull-up resistor; V_PG,L = 0.3V at 2mA.
7	BS	passive	Bootstrap capacitor pin supplying the high-side gate driver. Connect a 0.1μF ceramic capacitor between BS and LX. Abs max BS-LX = 6V.
8	LX	output	Switching node; drain of internal N-channel top FET (RDS(ON) 150mΩ). Connect to the external inductor and freewheeling Schottky diode. Handles up to 3A output; dynamic voltage rating VIN+3V to GND-5V for 10ns.
EP	EPAD	power_in	Exposed thermal pad on the bottom of the SO8E package. Must be connected to the GND pin and to the system ground plane for optimal thermal performance (θJA = 42°C/W, θJC = 4°C/W).

Key specifications

Parameter	Value
Manufacturer	Silergy Corp
Package	SOP-8-EP
Category	PMIC
Pins	9

Ordering variants

Same part, different packaging or reel option.

SY8513FCC

CAD (KiCad official)

Symbol: SY8513FCC
Footprint: Package_SO:Diodes_SO-8EP
3D model: SOP-8-EP (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`sy8513fcc.step`	194 KB	You want the bare part, or you mark your own boards.
`sy8513fcc-etched.step`	1.8 MB	You want the part with `SY8513FCC` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 446 faces against 63 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Silergy Corp datasheet (6 pp, sha256 6ddffce45b3660b0, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF