component

SY8513FCC

Public Made by Adom

by adom

Silergy Corp DC-DC Converters, SOP-8-EP. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206
Name Last commit message Last updated
docs sy8513fcc: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
package.json Publish 0.2.0 · Ray
pads.json add symbol pin "9" for the exposed thermal pad: the footprint carries the pad and the symbol had none, so it reached no… · Ray
page.json sy8513fcc: specified limits as data (metadata.characteristics, 42 rows from the datasheet) · Ray
README.md sy8513fcc: specified limits as data (metadata.characteristics, 42 rows from the datasheet) · Ray
sy8513fcc-etched.fit.json sy8513fcc: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
sy8513fcc-etched.glb sy8513fcc: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
sy8513fcc-etched.step sy8513fcc: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
sy8513fcc.glb fix footprint: SOIC-8_3.9x4.9mm_P1.27mm -> Diodes_SO-8EP (ep_dropped, 8 pins; datasheet EP 3.4x2.55mm, land 2.613x3.502… · Ray
sy8513fcc.kicad_mod fix footprint: SOIC-8_3.9x4.9mm_P1.27mm -> Diodes_SO-8EP (ep_dropped, 8 pins; datasheet EP 3.4x2.55mm, land 2.613x3.502… · Ray
sy8513fcc.kicad_sym add symbol pin "9" for the exposed thermal pad: the footprint carries the pad and the symbol had none, so it reached no… · Ray
sy8513fcc.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
sy8513fcc.step fix footprint: SOIC-8_3.9x4.9mm_P1.27mm -> Diodes_SO-8EP (ep_dropped, 8 pins; datasheet EP 3.4x2.55mm, land 2.613x3.502… · Ray

SY8513FCC

Silergy Corp · DC-DC Converters · SOP-8-EP

SY8513FCC from Silergy Corp, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Input supply pin, 4.5V to 100V range (abs max 100V). Decouple to GND with at least a 1μF ceramic capacitor placed close to the pin.
2 EN input Enable control input. Pull high to turn on the converter (V_EN,R typ 1.1V rising, V_EN,F typ 0.9V falling). Do not leave floating. Abs max -0.3V to VIN+0.3V.
3 FS input Switching frequency programming pin. Connect a resistor from FS to GND to set fSW between 100kHz and 500kHz per fSW(kHz) = 1e5 / RFS(kΩ). RFS range 200kΩ to 1MΩ.
4 GND power_in Device ground reference. Tie to system ground plane; exposed pad must also be connected to this pin/ground.
5 FB input Output voltage feedback input to the error amplifier. Connect to the center tap of the output resistor divider to set VOUT = 0.8V × (1 + R1/R2). VREF = 0.8V ±1%; IFB ±50nA.
6 PG output Power-good indicator, open-drain output. Asserts (pulled low released to Hi-Z) when the FB voltage is within approximately 90% to 120% of the regulation point. Requires an external pull-up resistor; V_PG,L = 0.3V at 2mA.
7 BS passive Bootstrap capacitor pin supplying the high-side gate driver. Connect a 0.1μF ceramic capacitor between BS and LX. Abs max BS-LX = 6V.
8 LX output Switching node; drain of internal N-channel top FET (RDS(ON) 150mΩ). Connect to the external inductor and freewheeling Schottky diode. Handles up to 3A output; dynamic voltage rating VIN+3V to GND-5V for 10ns.
EP EPAD power_in Exposed thermal pad on the bottom of the SO8E package. Must be connected to the GND pin and to the system ground plane for optimal thermal performance (θJA = 42°C/W, θJC = 4°C/W).

Key specifications

Parameter Value
Manufacturer Silergy Corp
Package SOP-8-EP
Category PMIC
Pins 9

Ordering variants

Same part, different packaging or reel option.

  • SY8513FCC

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Voltage Range VIN 4.5 100 V 4
Input UVLO Threshold VUVLO 3.9 4.2 4.5 V 4
Quiescent Current IQ 100 130 µA VFB=VREF×105% 4
Shutdown Current ISHDN 2 8 16 µA VEN=0V 4
Feedback Reference Voltage VREF 792 800 808 mV 4
FB Input Current IFB -50 50 nA VFB=3.3V 4
EN Rising Threshold VEN,R 1 1.1 1.2 V 4
EN Falling Threshold VEN,F 0.8 0.9 1 V 4
EN Leakage Current IEN -1 1 µA 4
Switching Frequency Program Range fSW,RNG 100 500 kHz RFS=200k~1M 4
Switching Frequency Setting Accuracy fSW 400 500 600 kHz RFS=200k 4
Output Under Voltage Protection Threshold VUVP 45 50 55 %VREF 4
Supply Input Voltage (absolute maximum) -0.3 100 V 3
BS-LX Voltage -0.3 6 V 3
EN, FS, FB, PG, LX Voltage -0.3 V 3
Power Dissipation, SO8E PD 2.38 W TA = 25°C 3
Junction Temperature Range (absolute maximum) -40 150 °C 3
Lead Temperature (Soldering) 260 °C 10 sec. 3
Storage Temperature Range -65 150 °C 3
Supply Input Voltage (recommended) 4.5 100 V 3
Junction Temperature Range (recommended) -40 125 °C 3
Ambient Temperature Range -40 85 °C 3
Top FET On-Resistance RDS(ON) 150 mΩ 4
Min ON Time tON,MIN 180 ns 4
Min OFF Time tOFF,MIN 280 ns 4
Soft-start Time tSS 2 ms 4
Power Good Threshold (VFB falling, PG high to low) VPG 90 %VREF VFB falling, PG from high to low 4
Power Good Threshold (VFB rising, PG low to high) VPG 92 %VREF VFB rising, PG from low to high 4
Power Good Threshold (VFB rising, PG high to low) VPG 120 %VREF VFB rising, PG from high to low 4
Power Good Threshold (VFB falling, PG low to high) VPG 115 %VREF VFB falling, PG from low to high 4
Power Good Delay (high to low) tPG_F 20 µs 4
Power Good Delay (low to high) tPG_R 200 µs 4
Power Good Output Low VPG,L 0.3 V IPG=2mA 4
PG High Leakage Current 1 µA 4
Top FET Current Limit ILMT,RNG 3.8 A 4
Output UVP Delay tUVP,DLY 10 µs 4
UVP Hiccup ON Time tUVP,ON 2 ms 4
UVP Hiccup OFF Time tUVP,OFF 16 ms 4
Thermal Shutdown Temperature TSD 150 °C 4
Thermal Shutdown Hysteresis THYS 15 °C 4
Package Thermal Resistance, junction to ambient θJA 42 °C/W natural convection, TA = 25°C, two-layer Silergy demo board 3
Package Thermal Resistance, junction to case θJC 4 °C/W 3

CAD (KiCad official)

  • Symbol: SY8513FCC
  • Footprint: Package_SO:Diodes_SO-8EP
  • 3D model: SOP-8-EP (KiCad packages3D, STEP)
  • 3D model files: sy8513fcc-etched.step / sy8513fcc-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sy8513fcc.step / sy8513fcc.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
sy8513fcc.step 194 KB You want the bare part, or you mark your own boards.
sy8513fcc-etched.step 1.8 MB You want the part with SY8513FCC already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 446 faces against 63 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Silergy Corp datasheet (6 pp, sha256 6ddffce45b3660b0, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF