component
SY6355DBC
Public Unreviewedby Ray
Silergy Corp Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, DFN-10-EP(3x3). Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSY6355DBC
Silergy Corp · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · DFN-10-EP(3x3)
SY6355DBC from Silergy Corp, in a DFN-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | REFIN | input | Reference input. Connect to GND through a 0.1µF ceramic capacitor. Operating range 0.5V to 1.8V; REFIN UVLO ~390mV rising with ~20mV hysteresis. |
| 2 | VLDOIN | power_in | Supply voltage for the LDO output stage. Use a 10µF (or greater) ceramic capacitor to supply transient charge. Operating range -0.1V to 3.5V. |
| 3 | VO | power_out | Power output pin for the LDO (VTT). For stable operation, total output capacitance must be greater than 20µF; three 10µF ceramic capacitors in parallel are recommended to minimize ESR/ESL. Source/sink current limits ~3-5.5A. |
| 4 | PGND | power_in | Power ground pin for the LDO output stage. Operating range -0.1V to 0.1V relative to GND. |
| 5 | VOSNS | input | Voltage sense input for the LDO. Connect to the positive terminal of the output capacitor or load for remote sensing (Kelvin feedback). |
| 6 | REFOUT | output | Buffered reference output (VTTREF), ±10mA capable. Connect to GND through a 0.1µF ceramic capacitor. Output tracks REFIN (typ. tolerance ±12mV). |
| 7 | EN | input | Enable input. Driving high turns on the regulator; driving low shuts off the regulator and discharges VTT (RDSCHRG ~18Ω). For DDR VTT application, connect EN to SLP_S3. Do not leave floating. VIH ≥ 1.2V, VIL ≤ 0.3V. |
| 8 | GND | power_in | Signal ground pin. |
| 9 | PGOOD | output | Open-drain power-good indicator; pulled high (via external pull-up) when VO output is within ±20% of REFOUT. VOL ≤ 0.4V at 4mA sink; startup delay ~2ms; bad delay ~10µs. |
| 10 | VIN | power_in | Input supply pin. Requires a bulk capacitor close to the pin plus a 1µF-4.7µF ceramic decoupling capacitor to prevent input sag. Operating range 2.375V to 3.5V; UVLO wake-up typ. 2.3V. |
| 11 | EP | power_in | Exposed thermal pad. Connect to ground plane for better thermal performance. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Silergy Corp |
| Package | DFN-10-EP(3x3) |
| Category | PMIC |
| Pins | 11 |
Ordering variants
Same part, different packaging or reel option.
SY6355DBC
CAD (KiCad official)
- Symbol:
SY6355DBC - Footprint:
Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm - 3D model: DFN-10-EP(3x3) (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Silergy Corp datasheet (13 pp, sha256
8c8292e10f796fc9, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).