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SX1208IMLTRT

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by Ray

SEMTECH RF Transceiver ICs, QFN-24-EP(5x5). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

Schematic Symbol

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PCB Footprint

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Datasheet

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Contents

README

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SX1208IMLTRT

SEMTECH · RF Transceiver ICs · QFN-24-EP(5x5)

SX1208IMLTRT from SEMTECH, in a QFN-24-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
0 GROUND power_in Exposed ground pad on the underside of the QFN-24 package. Must be soldered to the PCB ground plane for both electrical return and thermal dissipation.
1 VBAT1 power_in Battery/main supply voltage input, 2.4-3.6 V operating (absolute max 3.9 V). Feeds the internal power distribution system alongside VBAT2.
2 VR_ANA power_out Regulated supply voltage output for analog circuitry. Requires an external decoupling capacitor to ground; do not drive externally.
3 VR_DIG power_out Regulated supply voltage output for the digital blocks. Requires an external decoupling capacitor to ground; do not drive externally.
4 XTA passive Crystal oscillator connection A. Connects to one terminal of the reference crystal (nominal 32 MHz) with load capacitors to ground.
5 XTB passive Crystal oscillator connection B. Connects to the second terminal of the 32 MHz reference crystal; can also be driven from a TCXO instead of a crystal.
6 RESET bidirectional Reset trigger input for chip POR/manual reset control. Bidirectional per pinout table; typically driven low to force a manual reset, then released to allow the chip to complete its power-on-reset sequence.
7 DIO0 bidirectional Software-configurable digital I/O. Function (IRQ source, data, clock, etc.) is selected by DIO mapping registers depending on Continuous or Packet mode.
8 DIO1/DCLK bidirectional Software-configurable digital I/O. In Continuous Mode this pin also serves as the data clock (DCLK) output for synchronous FSK/OOK data transfers.
9 DIO2/DATA bidirectional Software-configurable digital I/O. In Continuous Mode this pin also carries the serial DATA line for Tx/Rx bit-stream I/O.
10 DIO3 bidirectional Software-configurable digital I/O. Programmable IRQ / status output selectable via DIO mapping registers.
11 DIO4 bidirectional Software-configurable digital I/O. Programmable IRQ / status output selectable via DIO mapping registers.
12 DIO5 bidirectional Software-configurable digital I/O. Programmable IRQ / status output selectable via DIO mapping registers; commonly used as ClkOut when enabled.
13 VBAT2 power_in Second battery/main supply voltage input, 2.4-3.6 V operating (absolute max 3.9 V). Tie to VBAT1 on the PCB with local decoupling.
14 GND power_in Ground reference. Tie directly to the PCB ground plane along with the exposed pad.
15 SCK input SPI clock input from the host MCU. Clocks configuration and FIFO data on the 4-wire SPI interface described in section 5.2.1.
16 MISO output SPI serial data output to the host MCU. High-impedance when NSS is de-asserted.
17 MOSI input SPI serial data input from the host MCU. Sampled on the SCK edge defined by the SPI timing diagram (Figure 24).
18 NSS input SPI chip-select input (active low). Frames each SPI access; must be held low for the entire address+data transfer.
19 RXTX output Rx/Tx switch control output. Drives an external RF T/R switch to steer the antenna between the receiver and PA paths.
20 GND power_in Ground reference for the RF section. Tie to the PCB ground plane with a low-impedance connection.
21 RFIO bidirectional Bidirectional RF input/output. Connects the LNA input and PA0 output through an external matching network and T/R switch to the antenna over 290-510 MHz.
22 GND power_in Ground reference for the PA section. Tie to the PCB ground plane with a low-impedance connection.
23 PA_BOOST output Optional high-power PA output (up to +20 dBm). Used with an external matching network when the +17/+20 dBm boosted transmit path is required; may be left floating if unused.
24 VR_PA power_in Regulated supply for the internal power amplifier. Requires external decoupling; connected to the PA regulator/inductor network per the reference design.

Key specifications

Parameter Value
Manufacturer SEMTECH
Package QFN-24-EP(5x5)
Category RF And Wireless
Pins 25

Ordering variants

Same part, different packaging or reel option.

  • SX1208IMLTRT

CAD (KiCad official)

  • Symbol: SX1208IMLTRT
  • Footprint: Package_DFN_QFN:QFN-24-1EP_5x5mm_P0.65mm_EP3.2x3.2mm
  • 3D model: QFN-24-EP(5x5) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SEMTECH datasheet (86 pp, sha256 4fbfa8e417435d4a, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF