STUSB4500QTR from STMicroelectronics, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CC1DB	bidirectional	Dead battery enable on CC1 pin (HV AIO). Connect to CC1 if used, otherwise tie to ground. Must be grounded when dead battery mode is not supported.
2	CC1	bidirectional	Type-C configuration channel 1 (HV AIO). Connects to Type-C receptacle pin A5. HiZ during reset. Short-to-VBUS tolerant up to 22 V.
3	NC	unconnected	No connect. Leave floating.
4	CC2	bidirectional	Type-C configuration channel 2 (HV AIO). Connects to Type-C receptacle pin B5. HiZ during reset. Short-to-VBUS tolerant up to 22 V.
5	CC2DB	bidirectional	Dead battery enable on CC2 pin (HV AIO). Connect to CC2 if used, otherwise tie to ground. Must be grounded when dead battery mode is not supported.
6	RESET	input	Reset input, active high. Driven from the system.
7	SCL	input	I2C clock input. Requires external pull-up to the I2C bus supply.
8	SDA	bidirectional	I2C data input/output, active low open drain. Requires external pull-up to the I2C bus supply.
9	DISCH	bidirectional	Internal discharge path or external discharge path enable, active low open drain (HV AI/OD). When used as input, a series resistor is required to limit discharge current (max 500 mA). Can also drive an external discharge switch. Requires external pull-up.
10	GND	power_in	Ground reference for the device.
11	ATTACH	output	Attachment detection, active low open drain. Asserted when a valid source-to-sink connection or debug accessory is established. Requires external pull-up to MCU supply.
12	ADDR0	input	I2C device address setting (LSB). Static; tie to ground or external pull-up for address selection. Must be connected to ground if no MCU is connected.
13	ADDR1	input	I2C device address setting. Static; tie to ground or external pull-up for address selection. Must be connected to ground if no MCU is connected.
14	POWER_OK3	output	Power contract flag, active low open drain (low voltage). Reports PD contract negotiation status (behavior configured by NVM PWR_OK_CFG). External pull-up required.
15	GPIO	output	General purpose output, active low open drain. Function selectable via NVM GPIO_CFG (SW_CTRL_GPIO / ERROR_RECOVERY (default) / DEBUG / SINK_POWER). Requires external pull-up.
16	VBUS_EN_SNK	output	VBUS sink power path enable, active low high-voltage open drain. Drives an external PMOS gate directly to enable the incoming VBUS power path. Connects to power switch or power system with external pull-up.
17	A_B_SIDE	output	Cable orientation output, active low open drain. Selects the USB SuperSpeed MUX routing (HiZ = CC1 attached, 0 = CC2 attached). External pull-up required. Not required for USB 2.0 only designs.
18	VBUS_VS_DISCH	bidirectional	VBUS voltage sense, monitoring and discharge path (HV AI). Connect to VBUS on the receptacle side through a series resistor to limit discharge current (max 50 mA). Discharge activated on cable disconnect, PDO transitions to lower voltage, hard reset, and error recovery.
19	ALERT	output	I2C interrupt output, active low open drain. Requires external pull-up to the I2C master supply.
20	POWER_OK2	output	Power contract flag, active low high-voltage open drain. Can directly drive a PMOS transistor to enable a power path (behavior configured by NVM PWR_OK_CFG). External pull-up required.
21	VREG_1V2	power_out	1.2 V internal LDO regulator output. External decoupling only; typical 1 µF (0.5 µF min., 10 µF max.) capacitor to ground.
22	VSYS	power_in	Low-voltage power supply from the system, VSYS = 3.0 V to 5.5 V. Can be tied to a single-cell Li battery or a 3.3 V/5 V rail. Tie to ground if unused.
23	VREG_2V7	power_out	2.7 V internal LDO regulator output. External decoupling only; typical 1 µF (0.5 µF min., 10 µF max.) capacitor to ground.
24	VDD	power_in	High-voltage power supply from the USB VBUS line, VDD = 4.1 V to 22 V. Connect to the VBUS receptacle side for VBUS-powered applications.
EP	EP	power_in	Exposed thermal pad, internally connected to ground. Must be soldered to the ground plane.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	QFN-24-EP(4x4)
Category	Interface
Pins	25

Ordering variants

Same part, different packaging or reel option.

STUSB4500QTR
STUSB4500QTRBJR

CAD (KiCad official)

Symbol: STUSB4500QTR
Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm
3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`stusb4500qtr.step`	277 KB	You want the bare part, or you mark your own boards.
`stusb4500qtr-etched.step`	2.9 MB	You want the part with `STUSB4500QTR` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 701 faces against 158 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (43 pp, sha256 42c29d31fff30e88, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF