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stm8s903k3t6ctr
Public Unreviewedby Ray
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-32(7x7). Datasheet-verified pinout, KiCad symbol/footprint/3D.
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README
markdownSTM8S903K3T6CTR
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-32(7x7)
STM8S903K3T6CTR from STMicroelectronics, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NRST | input | Active-low device reset input with integrated pull-up. Drive low to reset the MCU. Also used by SWIM programming/debug entry sequence. |
| 2 | PA1/OSCIN | bidirectional | Port A1 GPIO / HSE crystal or external clock input (OSCIN). Standard-drive I/O with optional weak pull-up. In Halt/Active-halt PA1 is auto-configured as input with weak pull-up and cannot wake the device. |
| 3 | PA2/OSCOUT | bidirectional | Port A2 GPIO / HSE crystal oscillator output (OSCOUT). Standard-drive I/O with optional weak pull-up; drives the far end of the crystal when HSE is enabled. |
| 4 | VSS | power_in | Digital ground reference (0 V). Tie to the system ground plane. |
| 5 | VCAP | passive | Output of the internal 1.8 V core regulator. Requires an external stabilization capacitor to VSS (typically 1 µF ceramic). Do not use to supply external circuits. |
| 6 | VDD | power_in | Main digital supply, 2.95 V to 5.5 V. Decouple with 100 nF near the pin and a bulk capacitor on the VDD rail. |
| 7 | PA3/TIM5_CH3/[SPI_NSS]/[UART1_TX] | bidirectional | Port A3 high-sink I/O. Default alternate: TIM5 channel 3 (input capture / output compare / PWM). Remap options: SPI_NSS (AFR1=1) or UART1_TX (AFR1:0=11). |
| 8 | PF4/[UART1_RX] | bidirectional | Port F4 standard-drive I/O. Remap option: UART1_RX when AFR1:0=11. |
| 9 | PB7 | bidirectional | Port B7 standard-drive general-purpose I/O with optional weak pull-up and interrupt capability. |
| 10 | PB6 | bidirectional | Port B6 standard-drive general-purpose I/O with optional weak pull-up and interrupt capability. |
| 11 | PB5/I2C_SDA/[TIM1_BKIN] | bidirectional | Port B5 true open-drain I/O (no P-buffer, no pull-up, no VDD protection diode - external pull-up required). Default alternate: I2C data (SDA). Remap: TIM1 break input when AFR4=1. |
| 12 | PB4/I2C_SCL/[ADC_ETR] | bidirectional | Port B4 true open-drain I/O (no P-buffer / pull-up / protection diode). Default alternate: I2C clock (SCL). Remap: ADC external trigger when AFR4=1. |
| 13 | PB3/AIN3/TIM1_ETR | bidirectional | Port B3 high-sink I/O. Analog input 3 to the 10-bit ADC and TIM1 external trigger input. |
| 14 | PB2/AIN2/TIM1_CH3N | bidirectional | Port B2 high-sink I/O. Analog input 2 to the 10-bit ADC and TIM1 complementary (inverted) channel 3 output. |
| 15 | PB1/AIN1/TIM1_CH2N | bidirectional | Port B1 high-sink I/O. Analog input 1 to the 10-bit ADC and TIM1 complementary (inverted) channel 2 output. |
| 16 | PB0/AIN0/TIM1_CH1N | bidirectional | Port B0 high-sink I/O. Analog input 0 to the 10-bit ADC and TIM1 complementary (inverted) channel 1 output. |
| 17 | PE5/SPI_NSS/[TIM1_CH1N] | bidirectional | Port E5 high-sink I/O. Default alternate: SPI slave-select (NSS). Remap: TIM1 complementary channel 1 when AFR1:0=11. |
| 18 | PC1/TIM1_CH1/UART1_CK/[TIM1_CH2N] | bidirectional | Port C1 high-sink I/O. Default alternate: TIM1 channel 1 and UART1 clock output. Remap: TIM1 complementary channel 2 when AFR1:0=11. |
| 19 | PC2/TIM1_CH2/[TIM1_CH3N] | bidirectional | Port C2 high-sink I/O. Default alternate: TIM1 channel 2. Remap: TIM1 complementary channel 3 when AFR1:0=11. |
| 20 | PC3/TIM1_CH3/[TLI]/[TIM1_CH1N] | bidirectional | Port C3 high-sink I/O. Default alternate: TIM1 channel 3. Remap options: top-level interrupt (TLI, AFR3=1) or TIM1 complementary channel 1 (AFR7=1). |
| 21 | PC4/TIM1_CH4/CLK_CCO/[AIN2]/[TIM1_CH2N] | bidirectional | Port C4 high-sink I/O. Default alternates: TIM1 channel 4 and configurable clock output (CCO). Remap options: analog input 2 (AFR2=1) or TIM1 complementary channel 2 (AFR7=1). |
| 22 | PC5/SPI_SCK/[TIM5_CH1] | bidirectional | Port C5 high-sink I/O. Default alternate: SPI clock (SCK). Remap: TIM5 channel 1 when AFR0=1. |
| 23 | PC6/SPI_MOSI/[TIM1_CH1] | bidirectional | Port C6 high-sink I/O. Default alternate: SPI master-out/slave-in (MOSI). Remap: TIM1 channel 1 when AFR0=1. |
| 24 | PC7/SPI_MISO/[TIM1_CH2] | bidirectional | Port C7 high-sink I/O. Default alternate: SPI master-in/slave-out (MISO). Remap: TIM1 channel 2 when AFR0=1. |
| 25 | PD0/TIM1_BKIN/[CLK_CCO] | bidirectional | Port D0 high-sink I/O. Default alternate: TIM1 break input. Remap: configurable clock output (CCO) when AFR5=1. |
| 26 | PD1/SWIM | bidirectional | Port D1 high-sink I/O and single-wire interface module (SWIM) data pin for on-chip programming and non-intrusive debugging. PD1 is configured as input pull-up during reset and after reset release. |
| 27 | PD2/[AIN3]/[TIM5_CH3] | bidirectional | Port D2 high-sink I/O. Remap options: analog input 3 (AFR2=1) or TIM5 channel 3 (AFR1=1 or AFR1:0=11). |
| 28 | PD3/AIN4/TIM5_CH2/ADC_ETR | bidirectional | Port D3 high-sink I/O. Default alternates: analog input 4, TIM5 channel 2 and ADC external trigger. |
| 29 | PD4/TIM5_CH1/BEEP/[UART1_CK] | bidirectional | Port D4 high-sink I/O. Default alternates: TIM5 channel 1 and beeper output. Remap: UART1 clock (UART1_CK) when AFR2=1. |
| 30 | PD5/AIN5/UART1_TX | bidirectional | Port D5 high-sink I/O. Default alternates: analog input 5 and UART1 data transmit (TX). |
| 31 | PD6/AIN6/UART1_RX | bidirectional | Port D6 high-sink I/O. Default alternates: analog input 6 and UART1 data receive (RX). |
| 32 | PD7/TLI/[TIM1_CH4] | bidirectional | Port D7 high-sink I/O. Default alternate: top-level interrupt (TLI). Remap: TIM1 channel 4 when AFR6=1. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-32(7x7) |
| Category | MCU |
| Pins | 32 |
Ordering variants
STM8S903K3T6CTRSTM8S903K3T6CTRK3T3CSTM8S903K3T6CTRK3T3CTRSTM8S903K3T6CTRK3U6STM8S903K3T6CTRK3U6TRSTM8S903K3T6CTRK3U3STM8S903K3T6CTRK3U3TRSTM8S903K3T6CTRK3B6STM8S903K3T6CTRK3B3STM8S903K3T6CTRF3P6STM8S903K3T6CTRF3P6TRSTM8S903K3T6CTRF3P3STM8S903K3T6CTRF3P3TRSTM8S903K3T6CTRF3U6STM8S903K3T6CTRF3U6TRSTM8S903K3T6CTRF3U3STM8S903K3T6CTRF3U3TRSTM8S903K3T6CTRF3M6STM8S903K3T6CTRF3M6TR
CAD (KiCad official)
- Symbol:
STM8S903K3T6CTR - Footprint:
Package_QFP:LQFP-32_7x7mm_P0.8mm - 3D model: LQFP-32(7x7) (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (None pp, sha256
c6b66177ea6c826f, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).