STM8S207R8T6 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	NRST	input	Active-low reset input/output. Bidirectional with internal pull-up; drive low to reset the device.
2	PA1/OSCIN	bidirectional	Port A1 general-purpose I/O; alternate function OSCIN (external resonator/crystal input) for HSE oscillator.
3	PA2/OSCOUT	bidirectional	Port A2 general-purpose I/O; alternate function OSCOUT (external resonator/crystal output) for HSE oscillator.
4	VSSIO_1	power_in	I/O ground reference for the port banks. Tie to system ground.
5	VSS	power_in	Digital core ground. Tie to system ground.
6	VCAP	passive	Internal 1.8 V regulator output; requires an external decoupling capacitor to VSS (typ. 1 uF).
7	VDD	power_in	Digital core power supply, 2.95 V to 5.5 V. Decouple with a local capacitor.
8	VDDIO_1	power_in	I/O power supply for the first port bank, 2.95 V to 5.5 V. Decouple locally.
9	PA3/TIM2_CH3	bidirectional	Port A3 GPIO; default alternate function TIM2 channel 3. Remap to TIM3_CH1 via AFR1 option bit.
10	PA4/UART1_RX	bidirectional	Port A4 GPIO with high-sink capability; default alternate function UART1 receive.
11	PA5/UART1_TX	bidirectional	Port A5 GPIO with high-sink capability; default alternate function UART1 transmit.
12	PA6/UART1_CK	bidirectional	Port A6 GPIO with high-sink capability; default alternate function UART1 synchronous clock.
13	PF7/AIN15	bidirectional	Port F7 GPIO; alternate function ADC analog input 15 (AIN15).
14	PF6/AIN14	bidirectional	Port F6 GPIO; alternate function ADC analog input 14 (AIN14).
15	PF5/AIN13	bidirectional	Port F5 GPIO; alternate function ADC analog input 13 (AIN13).
16	PF4/AIN12	bidirectional	Port F4 GPIO; alternate function ADC analog input 12 (AIN12).
17	PF3/AIN11	bidirectional	Port F3 GPIO; alternate function ADC analog input 11 (AIN11).
18	VREF+	power_in	ADC positive reference voltage input. Tie to VDDA or an external precision reference.
19	VDDA	power_in	Analog power supply for the ADC and analog blocks. Decouple to VSSA.
20	VSSA	power_in	Analog ground reference for the ADC and analog blocks.
21	VREF-	power_in	ADC negative reference voltage. Tie to VSSA or the low side of an external reference.
22	PF0/AIN10	bidirectional	Port F0 GPIO; alternate function ADC analog input 10 (AIN10).
23	PB7/AIN7	bidirectional	Port B7 GPIO; alternate function ADC analog input 7 (AIN7).
24	PB6/AIN6	bidirectional	Port B6 GPIO; alternate function ADC analog input 6 (AIN6).
25	PB5/AIN5	bidirectional	Port B5 GPIO; ADC analog input 5. Remap to I2C_SDA (true open-drain) via AFR6 option bit.
26	PB4/AIN4	bidirectional	Port B4 GPIO; ADC analog input 4. Remap to I2C_SCL (true open-drain) via AFR6 option bit.
27	PB3/AIN3	bidirectional	Port B3 GPIO; ADC analog input 3. Remap to TIM1_ETR via AFR5 option bit.
28	PB2/AIN2	bidirectional	Port B2 GPIO; ADC analog input 2. Remap to TIM1_CH3N via AFR5 option bit.
29	PB1/AIN1	bidirectional	Port B1 GPIO; ADC analog input 1. Remap to TIM1_CH2N via AFR5 option bit.
30	PB0/AIN0	bidirectional	Port B0 GPIO; ADC analog input 0. Remap to TIM1_CH1N via AFR5 option bit.
31	PE7/AIN8	bidirectional	Port E7 GPIO; alternate function ADC analog input 8 (AIN8).
32	PE6/AIN9	bidirectional	Port E6 GPIO; alternate function ADC analog input 9 (AIN9).
33	PE5/SPI_NSS	bidirectional	Port E5 GPIO; alternate function SPI master/slave select (NSS).
34	PC1/TIM1_CH1	bidirectional	Port C1 GPIO with high-sink capability; alternate function TIM1 channel 1.
35	PC2/TIM1_CH2	bidirectional	Port C2 GPIO with high-sink capability; alternate function TIM1 channel 2.
36	PC3/TIM1_CH3	bidirectional	Port C3 GPIO with high-sink capability; alternate function TIM1 channel 3.
37	PC4/TIM1_CH4	bidirectional	Port C4 GPIO with high-sink capability; alternate function TIM1 channel 4.
38	PC5/SPI_SCK	bidirectional	Port C5 GPIO with high-sink capability; alternate function SPI clock (SCK).
39	VSSIO_2	power_in	I/O ground for the second port bank. Tie to system ground.
40	VDDIO_2	power_in	I/O power supply for the second port bank, 2.95 V to 5.5 V. Decouple locally.
41	PC6/SPI_MOSI	bidirectional	Port C6 GPIO with high-sink capability; alternate function SPI master-out/slave-in (MOSI).
42	PC7/SPI_MISO	bidirectional	Port C7 GPIO with high-sink capability; alternate function SPI master-in/slave-out (MISO).
43	PG0	bidirectional	Port G0 general-purpose I/O. (CAN_TX alternate function is available only on STM8S208xx variants; this is STM8S207xx.)
44	PG1	bidirectional	Port G1 general-purpose I/O. (CAN_RX alternate function is available only on STM8S208xx variants; this is STM8S207xx.)
45	PG2	bidirectional	Port G2 general-purpose I/O.
46	PG3	bidirectional	Port G3 general-purpose I/O.
47	PG4	bidirectional	Port G4 general-purpose I/O.
48	PI0	bidirectional	Port I0 general-purpose I/O.
49	PG5	bidirectional	Port G5 general-purpose I/O.
50	PG6	bidirectional	Port G6 general-purpose I/O.
51	PG7	bidirectional	Port G7 general-purpose I/O.
52	PE4	bidirectional	Port E4 general-purpose I/O with external interrupt capability.
53	PE3/TIM1_BKIN	bidirectional	Port E3 GPIO; alternate function TIM1 break input.
54	PE2/I2C_SDA	bidirectional	Port E2 with alternate function I2C data (SDA). True open-drain output (no P-buffer, no protection diode to VDD, no internal pull-up); requires an external pull-up.
55	PE1/I2C_SCL	bidirectional	Port E1 with alternate function I2C clock (SCL). True open-drain output; requires an external pull-up.
56	PE0/CLK_CCO	bidirectional	Port E0 GPIO with high-sink capability; alternate function configurable clock output (CCO).
57	PD0/TIM3_CH2	bidirectional	Port D0 GPIO with high-sink capability; default TIM3 channel 2. Remap to TIM1_BKIN [AFR3] or CLK_CCO [AFR2] via option bits.
58	PD1/SWIM	bidirectional	Port D1 GPIO with high-sink capability; alternate function SWIM single-wire debug/programming interface. Input pull-up during reset.
59	PD2/TIM3_CH1	bidirectional	Port D2 GPIO with high-sink capability; default TIM3 channel 1. Remap to TIM2_CH3 via AFR1 option bit.
60	PD3/TIM2_CH2	bidirectional	Port D3 GPIO with high-sink capability; default TIM2 channel 2. Remap to ADC_ETR via AFR0 option bit.
61	PD4/TIM2_CH1/BEEP	bidirectional	Port D4 GPIO with high-sink capability; default TIM2 channel 1. Remap to BEEP output via AFR7 option bit.
62	PD5/UART3_TX	bidirectional	Port D5 GPIO; alternate function UART3 transmit.
63	PD6/UART3_RX	bidirectional	Port D6 GPIO; alternate function UART3 receive. Pulled up by ROM bootloader during boot activation.
64	PD7/TLI	bidirectional	Port D7 GPIO; alternate function top-level interrupt (TLI). TIM1_CH4 [AFR4] remap is available only on the 44-pin package (reserved here).

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	LQFP-64(10x10)
Category	MCU
Pins	64

Ordering variants

Same part, different packaging or reel option.

STM8S207R8T6
STM8S207R8T6RBT6
STM8S207R8T6R6T6
STM8S207R8T6MBT6
STM8S207R8T6M8T6
STM8S207R8T6CBT6
STM8S207R8T6C8T6
STM8S207R8T6C6T6
STM8S207R8T6SBT6
STM8S207R8T6S8T6
STM8S207R8T6S6T6
STM8S207R8T6K8T6
STM8S207R8T6K6T6

CAD (KiCad official)

Symbol: STM8S207R8T6
Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
3D model: LQFP-64(10x10) (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`stm8s207r8t6.step`	847 KB	You want the bare part, or you mark your own boards.
`stm8s207r8t6-etched.step`	5.8 MB	You want the part with `STM8S207R8T6` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 1411 faces against 995 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (103 pp, sha256 9ab3f7b6dda7af91, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF