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STM8S105S4T6CTR

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by Ray

STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-44(10x10). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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STM8S105S4T6CTR

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-44(10x10)

STM8S105S4T6CTR from STMicroelectronics, in a LQFP-44(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NRST input Active-low device reset input with internal pull-up. Drive low to force MCU reset; leave high (or drive high) for normal operation.
2 PA1/OSCIN bidirectional GPIO Port A1 / crystal/resonator oscillator input (OSCIN). Connect to one lead of the HSE crystal when using an external oscillator, otherwise usable as a general-purpose I/O (floating/wpu, push-pull or open-drain, up to 2 MHz).
3 PA2/OSCOUT bidirectional GPIO Port A2 / crystal/resonator oscillator output (OSCOUT). Connect to the other lead of the HSE crystal or leave unused as GPIO.
4 VSSIO_1 power_in I/O ground return for I/O bank 1. Tie to the board ground plane with a decoupling capacitor pair near the paired VDDIO_1.
5 VSS power_in Digital core ground. Tie to the main ground plane.
6 VCAP passive Internal 1.8 V regulator stabilization capacitor node. Connect an external ceramic capacitor (typically 1 µF) between VCAP and VSS; do NOT drive externally.
7 VDD power_in Digital core supply, 2.95 V to 5.5 V. Decouple to VSS with a ceramic capacitor close to the pin.
8 VDDIO_1 power_in I/O supply for I/O bank 1, 2.95 V to 5.5 V. Decouple to VSSIO_1 with a ceramic capacitor.
9 PA4 bidirectional GPIO Port A4 with high-sink capability. Programmable input (floating/wpu, external interrupt) or output (fast/slow, push-pull or open-drain).
10 PA5 bidirectional GPIO Port A5 with high-sink capability. Standard STM8 I/O with programmable input/output modes.
11 PA6 bidirectional GPIO Port A6 with high-sink capability. Standard STM8 I/O with programmable input/output modes.
12 VDDA power_in Analog supply for the ADC and analog blocks, 2.95 V to 5.5 V. Filter from VDD with a ferrite bead and decouple to VSSA.
13 VSSA power_in Analog ground reference for the ADC. Tie to VSS at a single star point for best analog performance.
14 PB7/AIN7 bidirectional GPIO Port B7 or ADC analog input channel 7 (10-bit).
15 PB6/AIN6 bidirectional GPIO Port B6 or ADC analog input channel 6 (10-bit).
16 PB5/AIN5/[I2C_SDA] bidirectional GPIO Port B5 or ADC analog input channel 5. When AFR6 remap option bit is set, becomes I2C data (I2C_SDA).
17 PB4/AIN4/[I2C_SCL] bidirectional GPIO Port B4 or ADC analog input channel 4. When AFR6 remap option bit is set, becomes I2C clock (I2C_SCL).
18 PB3/AIN3/[TIM1_ETR] bidirectional GPIO Port B3 or ADC analog input channel 3. When AFR5 is set, becomes TIM1 external trigger input (TIM1_ETR).
19 PB2/AIN2/[TIM1_CH3N] bidirectional GPIO Port B2 or ADC analog input channel 2. When AFR5 is set, becomes TIM1 channel 3 complementary output (TIM1_CH3N).
20 PB1/AIN1/[TIM1_CH2N] bidirectional GPIO Port B1 or ADC analog input channel 1. When AFR5 is set, becomes TIM1 channel 2 complementary output (TIM1_CH2N).
21 PB0/AIN0/[TIM1_CH1N] bidirectional GPIO Port B0 or ADC analog input channel 0. When AFR5 is set, becomes TIM1 channel 1 complementary output (TIM1_CH1N).
22 PE6/AIN9 bidirectional GPIO Port E6 or ADC analog input channel 9. On this 44-pin package AIN9 cannot be used in ADC scan mode.
23 PE5/SPI_NSS/UART2_CK bidirectional GPIO Port E5 or SPI master/slave select (SPI_NSS). On the LQFP44 variant the UART2 synchronous clock (UART2_CK) is also routed here per the pinout diagram (Figure 4).
24 PC1/TIM1_CH1 bidirectional GPIO Port C1 with high-sink capability, or TIM1 channel 1 capture/compare (TIM1_CH1). Per Table 6 the UART2 synchronous clock (UART2_CK) is also multiplexed on this pin.
25 PC2/TIM1_CH2 bidirectional GPIO Port C2 with high-sink capability, or TIM1 channel 2 capture/compare (TIM1_CH2).
26 PC3/TIM1_CH3 bidirectional GPIO Port C3 with high-sink capability, or TIM1 channel 3 capture/compare (TIM1_CH3).
27 PC5/SPI_SCK bidirectional GPIO Port C5 with high-sink capability, or SPI clock (SPI_SCK) up to 8 Mbit/s.
28 VSSIO_2 power_in I/O ground return for I/O bank 2. Tie to the ground plane close to VDDIO_2.
29 VDDIO_2 power_in I/O supply for I/O bank 2, 2.95 V to 5.5 V. Decouple to VSSIO_2 with a ceramic capacitor.
30 PC6/SPI_MOSI bidirectional GPIO Port C6 with high-sink capability, or SPI master-out/slave-in data (SPI_MOSI).
31 PC7/SPI_MISO bidirectional GPIO Port C7 with high-sink capability, or SPI master-in/slave-out data (SPI_MISO).
32 PG0 bidirectional GPIO Port G0. Standard STM8 I/O with floating/pull-up input and push-pull/open-drain output (up to 2 MHz).
33 PG1 bidirectional GPIO Port G1. Standard STM8 I/O with floating/pull-up input and push-pull/open-drain output (up to 2 MHz).
34 PE2/I2C_SDA bidirectional GPIO Port E2 or I2C data line (I2C_SDA). True open-drain output (T) - no P-buffer, no weak pull-up and no protection diode to VDD; an external pull-up resistor to VDD is required for I2C operation. Fast-mode capable up to 400 kbit/s.
35 PE1/I2C_SCL bidirectional GPIO Port E1 or I2C clock line (I2C_SCL). True open-drain output (T); requires an external pull-up resistor to VDD. Up to 400 kbit/s.
36 PE0/CLK_CCO bidirectional GPIO Port E0 with high-sink capability, or configurable clock output (CLK_CCO). Can output any of the master clock sources for external synchronization.
37 PD0/TIM3_CH2/[TIM1_BKIN]/[CLK_CCO] bidirectional GPIO Port D0 with high-sink capability. Default alternate function is TIM3 channel 2. Remap via option bits: AFR3 → TIM1_BKIN (break input), AFR2 → CLK_CCO (AFR2 has priority over AFR3 if both are set).
38 PD1/SWIM bidirectional GPIO Port D1 with high-sink capability, or SWIM (single-wire interface module) data for on-chip programming and non-intrusive debug. Held in input pull-up during and after reset. Keep accessible on the target board for programming.
39 PD2/TIM3_CH1/[TIM2_CH3] bidirectional GPIO Port D2 with high-sink capability. Default alternate function TIM3 channel 1; when AFR1 is set the pin becomes TIM2_CH3 (paired with the PA3 remap).
40 PD3/TIM2_CH2/[ADC_ETR] bidirectional GPIO Port D3 with high-sink capability. Default alternate function TIM2 channel 2; when AFR0 is set the pin becomes ADC_ETR (external trigger input for the ADC).
41 PD4/TIM2_CH1/[BEEP] bidirectional GPIO Port D4 with high-sink capability. Default alternate function TIM2 channel 1; when AFR7 is set the pin becomes the BEEP output (fixed-frequency square wave from the beeper).
42 PD5/UART2_TX bidirectional GPIO Port D5 or UART2 data transmit (UART2_TX). Supports async, synchronous, Smartcard, IrDA and LIN modes.
43 PD6/UART2_RX bidirectional GPIO Port D6 or UART2 data receive (UART2_RX).
44 PD7/TLI/[TIM1_CH4] bidirectional GPIO Port D7 or top-level interrupt input (TLI). When AFR4 is set the pin becomes TIM1 channel 4 (TIM1_CH4).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-44(10x10)
Category MCU
Pins 44

Ordering variants

Same part, different packaging or reel option.

  • STM8S105S4T6CTR
  • STM8S105S4T6CTRS6T6
  • STM8S105S4T6CTRS4T3
  • STM8S105S4T6CTRS6T3
  • STM8S105S4T6CTRS6T6CTR
  • STM8S105S4T6CTRC4T6
  • STM8S105S4T6CTRC6T6
  • STM8S105S4T6CTRC4T3
  • STM8S105S4T6CTRC6T3
  • STM8S105S4T6CTRK4T6
  • STM8S105S4T6CTRK6T6
  • STM8S105S4T6CTRK4T3
  • STM8S105S4T6CTRK6T3
  • STM8S105S4T6CTRK4U6A
  • STM8S105S4T6CTRK6U6A

CAD (KiCad official)

  • Symbol: STM8S105S4T6CTR
  • Footprint: Package_QFP:LQFP-44_10x10mm_P0.8mm
  • 3D model: LQFP-44(10x10) (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
stm8s105s4t6ctr.step 591 KB You want the bare part, or you mark your own boards.
stm8s105s4t6ctr-etched.step 5.1 MB You want the part with STM8S105S4T6CTR already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 1241 faces against 695 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (124 pp, sha256 fe32941a395f42c2, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF