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STM8S105S4T6C
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-44(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTM8S105S4T6C
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-44(10x10)
STM8S105S4T6C from STMicroelectronics, in a LQFP-44(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NRST | bidirectional | Device reset input, open-drain capable, active low |
| 2 | PA1/OSC_IN | bidirectional | Port A pin 1, oscillator or external clock input |
| 3 | PA2/OSC_OUT | bidirectional | Port A pin 2, oscillator output or general I/O |
| 4 | VSSIO_1 | power_in | I/O ground power supply |
| 5 | VSS | power_in | Digital ground power supply |
| 6 | VCAP | passive | 1.8 V internal regulator capacitor pin, requires 470 nF to 3.3 µF external capacitor |
| 7 | VDD | power_in | Digital power supply, operating range 2.95 to 5.5 V |
| 8 | VDDIO_1 | power_in | I/O power supply pin |
| 9 | PA4 | bidirectional | Port A pin 4, general purpose I/O with high sink output |
| 10 | PA5 | bidirectional | Port A pin 5, general purpose I/O with high sink output |
| 11 | PA6 | bidirectional | Port A pin 6, general purpose I/O with high sink output |
| 12 | VDDA | power_in | Analog power supply for ADC |
| 13 | VSSA | power_in | Analog ground power supply |
| 14 | PB7/AIN7 | bidirectional | Port B pin 7, analog input 7 or general I/O |
| 15 | PB6/AIN6 | bidirectional | Port B pin 6, analog input 6 or general I/O |
| 16 | PB5/AIN5 | bidirectional | Port B pin 5, analog input 5 or I2C data line (SDA) with remap option |
| 17 | PB4/AIN4 | bidirectional | Port B pin 4, analog input 4 or I2C clock line (SCL) with remap option |
| 18 | PB3/AIN3 | bidirectional | Port B pin 3, analog input 3 or Timer 1 external trigger input with remap option |
| 19 | PB2/AIN2 | bidirectional | Port B pin 2, analog input 2 or Timer 1 complementary channel 3 output with remap option |
| 20 | PB1/AIN1 | bidirectional | Port B pin 1, analog input 1 or Timer 1 complementary channel 2 output with remap option |
| 21 | PB0/AIN0 | bidirectional | Port B pin 0, analog input 0 or Timer 1 complementary channel 1 output with remap option |
| 22 | PE6/AIN9 | bidirectional | Port E pin 6, analog input 9 or general I/O |
| 23 | PE5/SPI_NSS | bidirectional | Port E pin 5, SPI slave select (NSS) input or general I/O |
| 24 | PC1/TIM1_CH1/UART2_CK | bidirectional | Port C pin 1, Timer 1 channel 1 capture/compare, or UART2 synchronous clock |
| 25 | PC2/TIM1_CH2 | bidirectional | Port C pin 2, Timer 1 channel 2 capture/compare output |
| 26 | PC3/TIM1_CH3 | bidirectional | Port C pin 3, Timer 1 channel 3 capture/compare output |
| 27 | PC5/SPI_SCK | bidirectional | Port C pin 5, SPI clock line for master or slave mode |
| 28 | VSSIO_2 | power_in | I/O ground power supply |
| 29 | VDDIO_2 | power_in | I/O power supply pin |
| 30 | PC6/SPI_MOSI | bidirectional | Port C pin 6, SPI Master Out/Slave In (MOSI) data line |
| 31 | PC7/SPI_MISO | bidirectional | Port C pin 7, SPI Master In/Slave Out (MISO) data line |
| 32 | PG0 | bidirectional | Port G pin 0, general purpose I/O |
| 33 | PG1 | bidirectional | Port G pin 1, general purpose I/O |
| 34 | PE2/I2C_SDA | bidirectional | Port E pin 2, I2C serial data (SDA) line, true open-drain output |
| 35 | PE1/I2C_SCL | bidirectional | Port E pin 1, I2C serial clock (SCL) line, true open-drain output |
| 36 | PE0/CLK_CCO | bidirectional | Port E pin 0, configurable clock output for external clock distribution |
| 37 | PD0/TIM3_CH2 | bidirectional | Port D pin 0, Timer 3 channel 2 capture/compare, or Timer 1 break input/clock output with remap |
| 38 | PD1/SWIM | bidirectional | Port D pin 1, Single Wire Interface Module (SWIM) data line for programming and debugging |
| 39 | PD2/TIM3_CH1 | bidirectional | Port D pin 2, Timer 3 channel 1 or Timer 2 channel 3 capture/compare with remap option |
| 40 | PD3/TIM2_CH2 | bidirectional | Port D pin 3, Timer 2 channel 2 capture/compare or ADC external trigger input with remap |
| 41 | PD4/TIM2_CH1 | bidirectional | Port D pin 4, Timer 2 channel 1 capture/compare or beeper output with remap option |
| 42 | PD5/UART2_TX | output | Port D pin 5, UART2 transmit data output line |
| 43 | PD6/UART2_RX | input | Port D pin 6, UART2 receive data input line |
| 44 | PD7/TLI | input | Port D pin 7, top level interrupt input or Timer 1 channel 4 output with remap option |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-44(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 44 |
CAD (KiCad official)
- Symbol:
STM8S105S4T6C - Footprint:
Package_QFP:LQFP-44_10x10mm_P0.8mm - 3D model: LQFP-44(10x10) (KiCad packages3D, STEP)
- 3D model files:
stm8s105s4t6c-etched.step/stm8s105s4t6c-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm8s105s4t6c.step/stm8s105s4t6c.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (121 pp, sha256
b1007bc27bb78327, retrieved 2026-09-26, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).