component
STM8S105C6T6TR
Public Unreviewedby Ray
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads when scrolled away or the tab is hidden.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads when scrolled away or the tab is hidden.
PCB Footprint
Open full view ↗Loads on click. Unloads when scrolled away or the tab is hidden.
Datasheet
Open in new tab ↗Loads on click. Unloads when scrolled away or the tab is hidden.
Contents
README
markdownSTM8S105C6T6TR
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)
STM8S105C6T6TR from STMicroelectronics, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NRST | bidirectional | Active-low reset. Bidirectional with internal weak pull-up; asserted by internal reset sources and can be driven low externally. |
| 2 | PA1/OSCIN | bidirectional | Port A bit 1 GPIO. Alternate: external resonator/crystal oscillator input (HSE OSCIN). |
| 3 | PA2/OSCOUT | bidirectional | Port A bit 2 GPIO. Alternate: external resonator/crystal oscillator output (HSE OSCOUT). |
| 4 | VSSIO_1 | power_in | I/O ground reference for the first I/O supply domain. |
| 5 | VSS | power_in | Digital ground for the core. |
| 6 | VCAP | passive | 1.8 V internal regulator decoupling capacitor pin. Connect a low-ESR ceramic capacitor (typ. 1 µF) to VSS; do not drive externally. |
| 7 | VDD | power_in | Digital core power supply, 2.95 V to 5.5 V. |
| 8 | VDDIO_1 | power_in | I/O supply for the first I/O bank, 2.95 V to 5.5 V. |
| 9 | PA3/TIM2_CH3/[TIM3_CH1] | bidirectional | Port A bit 3 GPIO. Default alternate: Timer 2 channel 3. Remap alternate: Timer 3 channel 1 via AFR1. |
| 10 | PA4 | bidirectional | Port A bit 4 GPIO, high-sink capable output. |
| 11 | PA5 | bidirectional | Port A bit 5 GPIO, high-sink capable output. |
| 12 | PA6 | bidirectional | Port A bit 6 GPIO, high-sink capable output. |
| 13 | VDDA | power_in | Analog power supply for the 10-bit ADC and analog reference. |
| 14 | VSSA | power_in | Analog ground for the 10-bit ADC. |
| 15 | PB7/AIN7 | bidirectional | Port B bit 7 GPIO. Alternate: ADC analog input channel 7. |
| 16 | PB6/AIN6 | bidirectional | Port B bit 6 GPIO. Alternate: ADC analog input channel 6. |
| 17 | PB5/AIN5/[I2C_SDA] | bidirectional | Port B bit 5 GPIO. Default alternate: ADC analog input channel 5. Remap alternate: I2C SDA via AFR6. |
| 18 | PB4/AIN4/[I2C_SCL] | bidirectional | Port B bit 4 GPIO. Default alternate: ADC analog input channel 4. Remap alternate: I2C SCL via AFR6. |
| 19 | PB3/AIN3/[TIM1_ETR] | bidirectional | Port B bit 3 GPIO. Default alternate: ADC analog input channel 3. Remap alternate: TIM1 external trigger via AFR5. |
| 20 | PB2/AIN2/[TIM1_CH3N] | bidirectional | Port B bit 2 GPIO. Default alternate: ADC analog input channel 2. Remap alternate: TIM1 complementary channel 3N via AFR5. |
| 21 | PB1/AIN1/[TIM1_CH2N] | bidirectional | Port B bit 1 GPIO. Default alternate: ADC analog input channel 1. Remap alternate: TIM1 complementary channel 2N via AFR5. |
| 22 | PB0/AIN0/[TIM1_CH1N] | bidirectional | Port B bit 0 GPIO. Default alternate: ADC analog input channel 0. Remap alternate: TIM1 complementary channel 1N via AFR5. |
| 23 | PE7/AIN8 | bidirectional | Port E bit 7 GPIO. Alternate: ADC analog input channel 8. |
| 24 | PE6/AIN9 | bidirectional | Port E bit 6 GPIO. Alternate: ADC analog input channel 9. |
| 25 | PE5/SPI_NSS | bidirectional | Port E bit 5 GPIO. Alternate: SPI master/slave select (NSS). |
| 26 | PC1/TIM1_CH1/UART2_CK | bidirectional | Port C bit 1 GPIO, high-sink. Alternates: TIM1 channel 1 and UART2 synchronous clock output. |
| 27 | PC2/TIM1_CH2 | bidirectional | Port C bit 2 GPIO, high-sink. Alternate: TIM1 channel 2. |
| 28 | PC3/TIM1_CH3 | bidirectional | Port C bit 3 GPIO, high-sink. Alternate: TIM1 channel 3. |
| 29 | PC4/TIM1_CH4 | bidirectional | Port C bit 4 GPIO, high-sink. Alternate: TIM1 channel 4. |
| 30 | PC5/SPI_SCK | bidirectional | Port C bit 5 GPIO, high-sink. Alternate: SPI clock (SCK). |
| 31 | VSSIO_2 | power_in | I/O ground reference for the second I/O supply domain. |
| 32 | VDDIO_2 | power_in | I/O supply for the second I/O bank, 2.95 V to 5.5 V. |
| 33 | PC6/SPI_MOSI | bidirectional | Port C bit 6 GPIO, high-sink. Alternate: SPI master-out/slave-in (MOSI). |
| 34 | PC7/SPI_MISO | bidirectional | Port C bit 7 GPIO, high-sink. Alternate: SPI master-in/slave-out (MISO). |
| 35 | PG0 | bidirectional | Port G bit 0 GPIO. |
| 36 | PG1 | bidirectional | Port G bit 1 GPIO. |
| 37 | PE3/TIM1_BKIN | bidirectional | Port E bit 3 GPIO. Alternate: TIM1 break input. |
| 38 | PE2/I2C_SDA | bidirectional | Port E bit 2 GPIO with true open-drain output. Alternate: I2C data (SDA), up to 400 kbit/s. |
| 39 | PE1/I2C_SCL | bidirectional | Port E bit 1 GPIO with true open-drain output. Alternate: I2C clock (SCL), up to 400 kbit/s. |
| 40 | PE0/CLK_CCO | bidirectional | Port E bit 0 GPIO, high-sink. Alternate: configurable clock output (CCO). |
| 41 | PD0/TIM3_CH2/[TIM1_BKIN]/[CLK_CCO] | bidirectional | Port D bit 0 GPIO, high-sink. Default alternate: TIM3 channel 2. Remap alternates: TIM1_BKIN via AFR3, or CLK_CCO via AFR2. |
| 42 | PD1/SWIM | bidirectional | Port D bit 1 GPIO, high-sink. Alternate: SWIM single-wire debug/programming interface. |
| 43 | PD2/TIM3_CH1/[TIM2_CH3] | bidirectional | Port D bit 2 GPIO, high-sink. Default alternate: TIM3 channel 1. Remap alternate: TIM2 channel 3 via AFR1. |
| 44 | PD3/TIM2_CH2/[ADC_ETR] | bidirectional | Port D bit 3 GPIO, high-sink. Default alternate: TIM2 channel 2. Remap alternate: ADC external trigger via AFR0. |
| 45 | PD4/TIM2_CH1/[BEEP] | bidirectional | Port D bit 4 GPIO, high-sink. Default alternate: TIM2 channel 1. Remap alternate: BEEP output via AFR7. |
| 46 | PD5/UART2_TX | bidirectional | Port D bit 5 GPIO. Alternate: UART2 transmit data. |
| 47 | PD6/UART2_RX | bidirectional | Port D bit 6 GPIO. Alternate: UART2 receive data. |
| 48 | PD7/TLI/[TIM1_CH4] | bidirectional | Port D bit 7 GPIO. Default alternate: top-level interrupt (TLI). Remap alternate: TIM1 channel 4 via AFR4. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-48(7x7) |
| Category | MCU |
| Pins | 48 |
Ordering variants
Same part, different packaging or reel option.
STM8S105C6T6TRSTM8S105C6T6TRS6T6STM8S105C6T6TRK6T6STM8S105C6T6TRK4T6STM8S105C6T6TRK6U6STM8S105C6T6TRK6U6ASTM8S105C6T6TRK6B6
CAD (KiCad official)
- Symbol:
STM8S105C6T6TR - Footprint:
Package_QFP:LQFP-48_7x7mm_P0.5mm - 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
stm8s105c6t6tr.step |
617 KB | You want the bare part, or you mark your own boards. |
stm8s105c6t6tr-etched.step |
5.1 MB | You want the part with STM8S105C6T6TR already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 1248 faces against 747 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (127 pp, sha256
7e99700b64658b2a, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).