STM8S005C6T6TR from STMicroelectronics, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	NRST	input	Active-low reset input with internal weak pull-up. Drive low >=500 ns to reset the device.
2	PA1/OSCIN	bidirectional	General-purpose I/O Port A1; alternate function is external crystal/resonator input (OSCIN) for the HSE oscillator.
3	PA2/OSCOUT	bidirectional	General-purpose I/O Port A2; alternate function is external crystal/resonator output (OSCOUT) for the HSE oscillator.
4	VSSIO_1	power_in	I/O ground reference for the first I/O supply domain. Tie to system ground.
5	VSS	power_in	Digital ground reference for the STM8 core and digital peripherals.
6	VCAP	passive	Output of the internal 1.8 V core regulator. Requires an external stabilization capacitor (typ 1 uF) to VSS; do not connect to any external supply.
7	VDD	power_in	Digital core power supply, 2.95 V to 5.5 V.
8	VDDIO_1	power_in	I/O power supply for the first I/O bank, 2.95 V to 5.5 V. Bypass locally to VSSIO_1.
9	PA3/TIM2_CH3	bidirectional	Port A3 GPIO; default alternate function TIM2 channel 3. AFR1 remap makes it TIM3_CH1.
10	PA4	bidirectional	Port A4 GPIO with high-sink drive capability; fast/slow programmable output (O3).
11	PA5	bidirectional	Port A5 GPIO with high-sink drive capability; fast/slow programmable output (O3).
12	PA6	bidirectional	Port A6 GPIO with high-sink drive capability; fast/slow programmable output (O3).
13	VDDA	power_in	Analog power supply for the ADC. Tie to VDD through a ferrite bead or filter; range 2.95 V to 5.5 V.
14	VSSA	power_in	Analog ground reference for the ADC. Star-connect to VSS.
15	PB7/AIN7	bidirectional	Port B7 GPIO; alternate function ADC1 analog input channel 7.
16	PB6/AIN6	bidirectional	Port B6 GPIO; alternate function ADC1 analog input channel 6.
17	PB5/AIN5/I2C_SDA	bidirectional	Port B5 GPIO; default alternate function ADC1 analog input channel 5. Option bit AFR6 remaps this pin as I2C_SDA (I2C data).
18	PB4/AIN4/I2C_SCL	bidirectional	Port B4 GPIO; default alternate function ADC1 analog input channel 4. Option bit AFR6 remaps this pin as I2C_SCL (I2C clock).
19	PB3/AIN3/TIM1_ETR	bidirectional	Port B3 GPIO; default alternate function ADC1 analog input channel 3. Option bit AFR5 remaps as TIM1_ETR (external trigger).
20	PB2/AIN2/TIM1_CH3N	bidirectional	Port B2 GPIO; default alternate function ADC1 analog input channel 2. Option bit AFR5 remaps as TIM1_CH3N (complementary output).
21	PB1/AIN1/TIM1_CH2N	bidirectional	Port B1 GPIO; default alternate function ADC1 analog input channel 1. Option bit AFR5 remaps as TIM1_CH2N (complementary output).
22	PB0/AIN0/TIM1_CH1N	bidirectional	Port B0 GPIO; default alternate function ADC1 analog input channel 0. Option bit AFR5 remaps as TIM1_CH1N (complementary output).
23	PE7/AIN8	bidirectional	Port E7 GPIO; alternate function ADC1 analog input channel 8.
24	PE6/AIN9	bidirectional	Port E6 GPIO; alternate function ADC1 analog input channel 9.
25	PE5/SPI_NSS	bidirectional	Port E5 GPIO; alternate function SPI master/slave select (NSS).
26	PC1/TIM1_CH1/UART2_CK	bidirectional	Port C1 GPIO with high-sink drive; alternate functions TIM1 channel 1 or UART2 synchronous clock output.
27	PC2/TIM1_CH2	bidirectional	Port C2 GPIO with high-sink drive; alternate function TIM1 channel 2 (input capture / output compare / PWM).
28	PC3/TIM1_CH3	bidirectional	Port C3 GPIO with high-sink drive; alternate function TIM1 channel 3.
29	PC4/TIM1_CH4	bidirectional	Port C4 GPIO with high-sink drive; alternate function TIM1 channel 4.
30	PC5/SPI_SCK	bidirectional	Port C5 GPIO with high-sink drive; alternate function SPI clock (SCK).
31	VSSIO_2	power_in	I/O ground reference for the second I/O supply domain.
32	VDDIO_2	power_in	I/O power supply for the second I/O bank, 2.95 V to 5.5 V. Bypass locally to VSSIO_2.
33	PC6/SPI_MOSI	bidirectional	Port C6 GPIO with high-sink drive; alternate function SPI MOSI (master out / slave in).
34	PC7/SPI_MISO	bidirectional	Port C7 GPIO with high-sink drive; alternate function SPI MISO (master in / slave out).
35	PG0	bidirectional	Port G0 general-purpose I/O, standard drive (O1).
36	PG1	bidirectional	Port G1 general-purpose I/O, standard drive (O1).
37	PE3/TIM1_BKIN	bidirectional	Port E3 GPIO; alternate function TIM1 break input (BKIN) to force outputs to a safe state.
38	PE2/I2C_SDA	bidirectional	Port E2 GPIO; alternate function I2C data (SDA). True open-drain output (no P-buffer, no pull-up, no VDD protection diode) - requires external pull-up.
39	PE1/I2C_SCL	bidirectional	Port E1 GPIO; alternate function I2C clock (SCL). True open-drain output - requires external pull-up.
40	PE0/CLK_CCO	bidirectional	Port E0 GPIO with high-sink drive; alternate function configurable clock output (CLK_CCO) for the CPU/peripheral clock.
41	PD0/TIM3_CH2/TIM1_BKIN/CLK_CCO	bidirectional	Port D0 GPIO with high-sink drive; default alternate function TIM3 channel 2. Option bit AFR3 remaps to TIM1_BKIN; option bit AFR2 remaps to CLK_CCO.
42	PD1/SWIM	bidirectional	Port D1 GPIO with high-sink drive; alternate function SWIM (single-wire interface module) data line for programming and in-circuit debug. Pull-up applied during reset.
43	PD2/TIM3_CH1/TIM2_CH3	bidirectional	Port D2 GPIO with high-sink drive; default alternate function TIM3 channel 1. Option bit AFR1 remaps to TIM2_CH3.
44	PD3/TIM2_CH2/ADC_ETR	bidirectional	Port D3 GPIO with high-sink drive; default alternate function TIM2 channel 2. Option bit AFR0 remaps to ADC external trigger (ADC_ETR).
45	PD4/TIM2_CH1/BEEP	bidirectional	Port D4 GPIO with high-sink drive; default alternate function TIM2 channel 1. Option bit AFR7 remaps to BEEP output.
46	PD5/UART2_TX	bidirectional	Port D5 GPIO; alternate function UART2 data transmit (TX).
47	PD6/UART2_RX	bidirectional	Port D6 GPIO; alternate function UART2 data receive (RX).
48	PD7/TLI/TIM1_CH4	bidirectional	Port D7 GPIO; default alternate function TLI (top-level interrupt input). Option bit AFR4 remaps to TIM1 channel 4.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	LQFP-48(7x7)
Category	MCU
Pins	48

Ordering variants

Same part, different packaging or reel option.

STM8S005C6T6TR
STM8S005C6T6TRK6T6
STM8S005C6T6TRK6T6TR

CAD (KiCad official)

Symbol: STM8S005C6T6TR
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`stm8s005c6t6tr.step`	617 KB	You want the bare part, or you mark your own boards.
`stm8s005c6t6tr-etched.step`	5.2 MB	You want the part with `STM8S005C6T6TR` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 1278 faces against 747 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (97 pp, sha256 97b9faba420e5e3a, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF