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STM8L151K6T6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-32(7x7)

STM8L151K6T6 from STMicroelectronics, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NRST/PA1 bidirectional Active-low device reset (Schmitt-trigger input, internal weak pull-up). At power-up this pin is a reset input with pull-up; it may be reconfigured as general-purpose Port A1 output (open-drain or push-pull only - not usable as GPI).
2 PA2/OSC_IN/[USART1_TX]/[SPI1_MISO] bidirectional High-sink GPIO PA2, or HSE crystal oscillator input (1-16 MHz). Optionally remappable as USART1 TX or SPI1 MISO.
3 PA3/OSC_OUT/[USART1_RX]/[SPI1_MOSI] bidirectional High-sink GPIO PA3, or HSE crystal oscillator output. Optionally remappable as USART1 RX or SPI1 MOSI.
4 PA4/TIM2_BKIN/[TIM2_ETR]/LCD_COM0/ADC1_IN2/COMP1_INP bidirectional 3.6 V-tolerant high-sink GPIO PA4 with multiplexed TIM2 break input, optional TIM2 external trigger, LCD COM0 (STM8L152 devices), ADC1 channel 2, and comparator 1 positive input.
5 PA5/TIM3_BKIN/[TIM3_ETR]/LCD_COM1/ADC1_IN1/COMP1_INP bidirectional 3.6 V-tolerant high-sink GPIO PA5 with multiplexed TIM3 break input, optional TIM3 external trigger, LCD COM1, ADC1 channel 1, and comparator 1 positive input.
6 PA6/[ADC1_TRIG]/LCD_COM2/ADC1_IN0/COMP1_INP bidirectional 3.6 V-tolerant high-sink GPIO PA6 with optional ADC1 external trigger, LCD COM2, ADC1 channel 0, and comparator 1 positive input.
7 VSS1/VSSA/VREF- power_in Common ground for I/O supply, analog supply, and ADC1 negative reference. Tie directly to system 0 V.
8 VDD1/VDDA/VREF+ power_in Combined digital I/O supply, analog supply, and ADC1 positive voltage reference. Operating range 1.8 V to 3.6 V (down to 1.65 V at power down). Decouple with 100 nF close to the pin.
9 VLCD passive LCD booster external capacitor pin (STM8L152 devices with LCD). On STM8L151 (no LCD) it should be left as advised for the variant - see review_required.
10 PD1/TIM1_CH3N/[TIM3_ETR]/LCD_COM3/ADC1_IN21/COMP2_INP/COMP1_INP bidirectional 3.6 V-tolerant high-sink GPIO PD1 with TIM1 inverted channel 3, optional TIM3 external trigger, LCD COM3, ADC1 channel 21, and comparator 1/2 positive input.
11 PD2/TIM1_CH1/LCD_SEG8/ADC1_IN20/COMP1_INP bidirectional 3.6 V-tolerant high-sink GPIO PD2 with TIM1 channel 1, LCD segment 8, ADC1 channel 20, and comparator 1 positive input.
12 PD3/TIM1_ETR/LCD_SEG9/ADC1_IN19/COMP1_INP bidirectional 3.6 V-tolerant high-sink GPIO PD3 with TIM1 external trigger, LCD segment 9, ADC1 channel 19, and comparator 1 positive input.
13 PB0/TIM2_CH1/LCD_SEG10/ADC1_IN18/COMP1_INP bidirectional 3.6 V-tolerant high-sink GPIO PB0 with TIM2 channel 1, LCD segment 10, ADC1 channel 18, and comparator 1 positive input. Internal pull-up asserted during reset; input floating after reset release.
14 PB1/TIM3_CH1/LCD_SEG11/ADC1_IN17/COMP1_INP bidirectional 3.6 V-tolerant high-sink GPIO PB1 with TIM3 channel 1, LCD segment 11, ADC1 channel 17, and comparator 1 positive input.
15 PB2/TIM2_CH2/LCD_SEG12/ADC1_IN16/COMP1_INP bidirectional 3.6 V-tolerant high-sink GPIO PB2 with TIM2 channel 2, LCD segment 12, ADC1 channel 16, and comparator 1 positive input.
16 PB3/[TIM2_ETR]/TIM1_CH2N/LCD_SEG13/ADC1_IN15/COMP1_INP bidirectional 3.6 V-tolerant high-sink GPIO PB3 with optional TIM2 external trigger, TIM1 inverted channel 2, LCD segment 13, ADC1 channel 15, and comparator 1 positive input.
17 PB4/[SPI1_NSS]/LCD_SEG14/ADC1_IN14/COMP1_INP/DAC_OUT bidirectional 3.6 V-tolerant high-sink GPIO PB4 with optional SPI1 chip-select, LCD segment 14, ADC1 channel 14, DAC output, and comparator 1 positive input. Internal pull-up asserted during reset; input floating after reset release.
18 PB5/[SPI1_SCK]/LCD_SEG15/ADC1_IN13/DAC_OUT/COMP1_INP bidirectional 3.6 V-tolerant high-sink GPIO PB5 with optional SPI1 clock, LCD segment 15, ADC1 channel 13, DAC output, and comparator 1 positive input.
19 PB6/[SPI1_MOSI]/LCD_SEG16/ADC1_IN12/COMP1_INP/DAC_OUT bidirectional 3.6 V-tolerant high-sink GPIO PB6 with optional SPI1 MOSI, LCD segment 16, ADC1 channel 12, DAC output, and comparator 1 positive input.
20 PB7/[SPI1_MISO]/LCD_SEG17/ADC1_IN11/COMP1_INP bidirectional 3.6 V-tolerant high-sink GPIO PB7 with optional SPI1 MISO, LCD segment 17, ADC1 channel 11, and comparator 1 positive input.
21 PD4/TIM1_CH2/LCD_SEG18/ADC1_IN10/COMP1_INP bidirectional 3.6 V-tolerant high-sink GPIO PD4 with TIM1 channel 2, LCD segment 18, ADC1 channel 10, and comparator 1 positive input.
22 PD5/TIM1_CH3/LCD_SEG19/ADC1_IN9/COMP1_INP bidirectional 3.6 V-tolerant high-sink GPIO PD5 with TIM1 channel 3, LCD segment 19, ADC1 channel 9, and comparator 1 positive input.
23 PD6/TIM1_BKIN/LCD_SEG20/ADC1_IN8/RTC_CALIB/VREFINT/COMP1_INP bidirectional 3.6 V-tolerant high-sink GPIO PD6 with TIM1 break input, LCD segment 20, ADC1 channel 8, RTC calibration output, internal voltage-reference output, and comparator 1 positive input.
24 PD7/TIM1_CH1N/LCD_SEG21/ADC1_IN7/RTC_ALARM/VREFINT/COMP1_INP bidirectional 3.6 V-tolerant high-sink GPIO PD7 with TIM1 inverted channel 1, LCD segment 21, ADC1 channel 7, RTC alarm output, internal voltage-reference output, and comparator 1 positive input.
25 PC0/I2C1_SDA bidirectional True open-drain I2C1 data (5 V tolerant, fast-mode 400 kHz, SMBus/PMBus capable) or general-purpose PC0. As a true open-drain pin, the P-buffer, weak pull-up, and protection diode to VDD are not implemented - external pull-up required.
26 PC1/I2C1_SCL bidirectional True open-drain I2C1 clock (5 V tolerant, fast-mode 400 kHz, SMBus/PMBus capable) or general-purpose PC1. External pull-up required.
27 PC2/USART1_RX/LCD_SEG22/ADC1_IN6/COMP1_INP/VREFINT bidirectional 3.6 V-tolerant high-sink GPIO PC2 with USART1 receive, LCD segment 22, ADC1 channel 6, internal voltage reference output, and comparator 1 positive input.
28 PC3/USART1_TX/LCD_SEG23/ADC1_IN5/COMP1_INP/COMP2_INM bidirectional 3.6 V-tolerant high-sink GPIO PC3 with USART1 transmit, LCD segment 23, ADC1 channel 5, comparator 2 negative input, and comparator 1 positive input.
29 PC4/USART1_CK/I2C1_SMB/CCO/LCD_SEG24/ADC1_IN4/COMP2_INM/COMP1_INP bidirectional 3.6 V-tolerant high-sink GPIO PC4 with USART1 synchronous clock, I2C1 SMBus alert, configurable clock output (CCO), LCD segment 24, ADC1 channel 4, and comparator 1/2 inputs.
30 PC5/OSC32_IN/[SPI1_NSS]/[USART1_TX] bidirectional High-sink GPIO PC5 or 32.768 kHz LSE crystal oscillator input; optional remap targets for SPI1 NSS or USART1 TX.
31 PC6/OSC32_OUT/[SPI1_SCK]/[USART1_RX] bidirectional High-sink GPIO PC6 or 32.768 kHz LSE crystal oscillator output; optional remap targets for SPI1 SCK or USART1 RX.
32 PA0/[USART1_CK]/SWIM/BEEP/IR_TIM bidirectional PA0 with 5 V-tolerant, high-sink LED-driver-capable I/O. Primary function is SWIM single-wire in-circuit debug/programming; also drives BEEP output, infrared timer output, or (via remap) USART1 synchronous clock. In input pull-up during and after reset release.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-32(7x7)
Category MCU
Pins 32

Ordering variants

  • STM8L151K6T6
  • STM8L151K6T6TR
  • STM8L151K6T6STM8L151K4T6
  • STM8L151K6T6STM8L151K6U6
  • STM8L151K6T6STM8L151K4U6
  • STM8L151K6T6STM8L151C6T6
  • STM8L151K6T6STM8L151C4T6
  • STM8L151K6T6STM8L151C6U6
  • STM8L151K6T6STM8L151C4U6
  • STM8L151K6T6STM8L151G6U6
  • STM8L151K6T6STM8L151G4U6
  • STM8L151K6T6STM8L151G6Y6
  • STM8L151K6T6STM8L151G4Y6

CAD (KiCad official)

  • Symbol: STM8L151K6T6
  • Footprint: Package_QFP:LQFP-32_7x7mm_P0.8mm
  • 3D model: LQFP-32(7x7) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (None pp, sha256 bdb8147fe7e55153, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

Schematic Symbol

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