component
STM706TAM6F
Public Unreviewedby Ray
STMicroelectronics Supervisor and Reset ICs, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads when scrolled away or the tab is hidden.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads when scrolled away or the tab is hidden.
PCB Footprint
Open full view ↗Loads on click. Unloads when scrolled away or the tab is hidden.
Datasheet
Open in new tab ↗Loads on click. Unloads when scrolled away or the tab is hidden.
README
markdownSTM706TAM6F
STMicroelectronics · Supervisor and Reset ICs · SOIC-8
STM706TAM6F from STMicroelectronics, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MR | input | Active-low manual (push-button) reset input. Internal ~40 kΩ pull-up to VCC; may be driven by TTL/CMOS or open-drain, or shorted to GND by a momentary switch. Asserting MR low forces RST low; reset remains asserted while MR is low and for trec (~200 ms typ) after MR returns high. Leave open if unused; add 0.1 µF to GND for noisy environments. |
| 2 | VCC | power_in | Positive supply input (nominal 3 V rail monitored by the VRST comparator). Typical operating range 2.7-5.5 V; supply current ~40 µA typ (no load). Decouple with 0.1 µF to VSS close to the pin. |
| 3 | VSS | power_in | Device ground reference (0 V). Common return for VCC decoupling, PFI divider, and MR debounce cap. |
| 4 | PFI | input | Power-fail comparator input. Compared to an internal VPFI reference (~1.25 V typ, independent of VRST); when PFI < VPFI, PFO goes low. Typically driven by a resistor divider from the unregulated pre-regulator rail to give early warning of impending VCC droop. Tie to VSS if the power-fail comparator is unused. |
| 5 | PFO | output | Active-low power-fail comparator output, push-pull. Goes low when PFI < VPFI, otherwise high. Intended to drive an MCU NMI/IRQ; do not force externally. MR is internally gated off while PFO is asserted low. Leave open if unused. |
| 6 | WDI | input | Watchdog input. The MCU must produce a rising or falling edge on WDI within the 1.6 s watchdog timeout to service the watchdog; a stuck-high or stuck-low condition for 1.6 s causes WDO to assert. Detects pulses as short as 50 ns. Float (or tri-state) the pin to disable the watchdog (leakage < 10 µA, load ≤ 200 pF). |
| 7 | RST | output | Active-low reset output (open in high state on STM706T is push-pull per datasheet). Pulses low for trec (~200 ms typ) whenever VCC falls below VRST (3.00-3.15 V), MR is asserted, or the watchdog times out (through WDO→MR external connection). Guaranteed valid low down to VCC = 1.0 V; add a ~100 kΩ pulldown for valid state below 1.0 V. |
| 8 | WDO | output | Active-low watchdog output, push-pull. Goes low when WDI shows no transition within 1.6 s, or when VCC falls below VRST, or when MR is asserted. Remains low until WDI transitions (watchdog serviced) or MR goes low. Returns high as soon as VCC exceeds VRST (unlike RST which is held for trec). To wire watchdog timeout as a reset source, connect WDO to MR. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SOIC-8 |
| Category | PMIC |
| Pins | 8 |
Ordering variants
Same part, different packaging or reel option.
STM706TAM6FSTM706TAM6FDS6F
CAD (KiCad official)
- Symbol:
STM706TAM6F - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (32 pp, sha256
fe2adb0e76018e05, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).