component
STM706PM6F
Public Unreviewedby Ray
STMicroelectronics Supervisor and Reset ICs, SO-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTM706PM6F
STMicroelectronics · Supervisor and Reset ICs · SO-8
STM706PM6F from STMicroelectronics, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MR | input | Active-low push-button/manual reset input. A logic low on MR asserts the reset output; reset remains asserted while MR is low and for t_rec (~200 ms typ.) after MR returns high. Has an internal pull-up; may be driven by TTL/CMOS logic or shorted to ground via a switch. Leave open if unused. |
| 2 | VCC | power_in | Supply voltage input monitored by the reset comparator. Typical operating range covers the 3 V supervisor threshold; recommended 0.1 µF bypass capacitor to VSS. |
| 3 | VSS | power_in | Ground / device return. |
| 4 | PFI | input | Power-fail comparator input. When PFI is less than V_PFI (~1.25 V internal reference), PFO is driven low; otherwise PFO remains high. Typically driven from a resistor divider on the unregulated pre-regulator supply for early brown-out warning. Connect to ground if unused. |
| 5 | PFO | output | Active-low power-fail output, push-pull. Goes low when PFI drops below V_PFI. Typically drives the microprocessor NMI/IRQ line for early power-loss warning. MR input is gated off while PFO is forced low. Leave open if unused. |
| 6 | WDI | input | Watchdog input. If WDI stays static (high or low) for 1.6 s (typ.), the internal watchdog timer expires and asserts WDO (and reset when WDO is tied to MR). Any rising or falling edge on WDI clears the timer. Watchdog can be disabled by allowing WDI to float (D-suffix parts only). |
| 7 | RST | output | Active-high reset output (STM706P variant). Pulses high for t_rec (~200 ms typ.) when triggered, and stays high while VCC is above the reset threshold and MR is high. Held high for t_rec after VCC falls below the reset threshold, the watchdog trips, or MR transitions high-to-low. Active-high polarity is unique to the STM706P; other family members provide active-low /RST here. |
| 8 | WDO | output | Active-low watchdog output, push-pull. Goes low when no transition occurs on WDI within 1.6 s, or when MR is asserted; remains low until a WDI edge or until VCC exceeds the reset threshold (WDO goes high as soon as VCC recovers, unlike RST which has a t_rec delay). Tie to MR if a watchdog timeout should also trigger a full reset. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SO-8 |
| Category | PMIC |
| Pins | 8 |
Ordering variants
Same part, different packaging or reel option.
STM706PM6FSTM706PM6FDS
CAD (KiCad official)
- Symbol:
STM706PM6F - Footprint:
Package_SO:TI_SO-PowerPAD-8 - 3D model: SO-8 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (32 pp, sha256
fe2adb0e76018e05, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).