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stm32l433rct6tr

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by Ray

STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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STM32L433RCT6TR

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

STM32L433RCT6TR from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup power supply for the RTC, LSE oscillator and backup registers. 1.55 V to 3.6 V. Ties to VDD when battery backup is not used.
2 PC13 bidirectional 5 V tolerant general-purpose I/O in the backup (VBAT) domain. Alt: EVENTOUT. Additional: RTC_TAMP1/RTC_TS/RTC_OUT/WKUP2. Limited drive: max 2 MHz, 30 pF, not for LED sourcing.
3 PC14-OSC32_IN bidirectional 5 V tolerant GPIO (PC14) also acting as LSE 32.768 kHz crystal input (OSC32_IN). Backup-domain I/O with limited drive.
4 PC15-OSC32_OUT bidirectional 5 V tolerant GPIO (PC15) also acting as LSE 32.768 kHz crystal output (OSC32_OUT). Backup-domain I/O with limited drive.
5 PH0-OSC_IN bidirectional 5 V tolerant GPIO (PH0) also acting as HSE crystal / external clock input (OSC_IN). Alt: EVENTOUT.
6 PH1-OSC_OUT bidirectional 5 V tolerant GPIO (PH1) also acting as HSE crystal output (OSC_OUT). Alt: EVENTOUT.
7 NRST bidirectional Bidirectional reset with internal weak pull-up. Active-low external reset input; also driven low internally on any reset source.
8 PC0 bidirectional 5 V tolerant Fm+/LCD/analog GPIO. Alt: LPTIM1_IN1, I2C3_SCL, LPUART1_RX, LCD_SEG18, LPTIM2_IN1, EVENTOUT. Additional: ADC1_IN1.
9 PC1 bidirectional 5 V tolerant Fm+/LCD/analog GPIO. Alt: LPTIM1_OUT, I2C3_SDA, LPUART1_TX, LCD_SEG19, EVENTOUT. Additional: ADC1_IN2.
10 PC2 bidirectional 5 V tolerant LCD/analog GPIO. Alt: LPTIM1_IN2, SPI2_MISO, LCD_SEG20, EVENTOUT. Additional: ADC1_IN3.
11 PC3 bidirectional 5 V tolerant analog-capable GPIO. Alt: LPTIM1_ETR, SPI2_MOSI, LCD_VLCD, SAI1_SD_A, LPTIM2_ETR, EVENTOUT. Additional: ADC1_IN4.
12 VSSA/VREF- power_in Analog ground and ADC/DAC negative reference. Tie to VSS; combined into a single pin on LQFP64.
13 VDDA/VREF+ power_in Analog supply and ADC/DAC positive reference (1.62 V to 3.6 V, upper bound tracks VDD). Combined into a single pin on LQFP64. Decouple to VSSA with 100 nF + 1 µF.
14 PA0 bidirectional 5 V tolerant analog-capable GPIO. Alt: TIM2_CH1, USART2_CTS, COMP1_OUT, SAI1_EXTCLK, TIM2_ETR, EVENTOUT. Additional: OPAMP1_VINP, COMP1_INM, ADC1_IN5, RTC_TAMP2/WKUP1.
15 PA1 bidirectional 5 V tolerant LCD/analog-capable GPIO. Alt: TIM2_CH2, I2C1_SMBA, SPI1_SCK, USART2_RTS_DE, LCD_SEG0, TIM15_CH1N, EVENTOUT. Additional: OPAMP1_VINM, COMP1_INP, ADC1_IN6.
16 PA2 bidirectional 5 V tolerant LCD/analog-capable GPIO. Alt: TIM2_CH3, USART2_TX, LPUART1_TX, QUADSPI_BK1_NCS, LCD_SEG1, COMP2_OUT, TIM15_CH1, EVENTOUT. Additional: COMP2_INM, ADC1_IN7, WKUP4/LSCO.
17 PA3 bidirectional 3.6 V tolerant LCD/analog-capable GPIO (TT_la). Alt: TIM2_CH4, USART2_RX, LPUART1_RX, QUADSPI_CLK, LCD_SEG2, SAI1_MCLK_A, TIM15_CH2, EVENTOUT. Additional: OPAMP1_VOUT, COMP2_INP, ADC1_IN8.
18 VSS power_in Digital ground reference. All VSS pins must be tied together.
19 VDD power_in Digital I/O and core regulator supply, 1.71 V to 3.6 V. Decouple each VDD to VSS with 100 nF; single bulk cap of 4.7 µF near the die.
20 PA4 bidirectional 3.6 V tolerant analog-capable GPIO (TT_a). Alt: SPI1_NSS, SPI3_NSS, USART2_CK, SAI1_FS_B, LPTIM2_OUT, EVENTOUT. Additional: COMP1_INM, COMP2_INM, ADC1_IN9, DAC1_OUT1.
21 PA5 bidirectional 3.6 V tolerant analog-capable GPIO (TT_a). Alt: TIM2_CH1, TIM2_ETR, SPI1_SCK, LPTIM2_ETR, EVENTOUT. Additional: COMP1_INM, COMP2_INM, ADC1_IN10, DAC1_OUT2.
22 PA6 bidirectional 5 V tolerant LCD/analog-capable GPIO. Alt: TIM1_BKIN, SPI1_MISO, COMP1_OUT, USART3_CTS, LPUART1_CTS, QUADSPI_BK1_IO3, LCD_SEG3, TIM1_BKIN_COMP2, TIM16_CH1, EVENTOUT. Additional: ADC1_IN11.
23 PA7 bidirectional 5 V tolerant Fm+/LCD/analog-capable GPIO. Alt: TIM1_CH1N, I2C3_SCL, SPI1_MOSI, QUADSPI_BK1_IO2, LCD_SEG4, COMP2_OUT, EVENTOUT. Additional: ADC1_IN12.
24 PC4 bidirectional 5 V tolerant LCD/analog-capable GPIO. Alt: USART3_TX, LCD_SEG22, EVENTOUT. Additional: COMP1_INM, ADC1_IN13.
25 PC5 bidirectional 5 V tolerant LCD/analog-capable GPIO. Alt: USART3_RX, LCD_SEG23, EVENTOUT. Additional: COMP1_INP, ADC1_IN14, WKUP5.
26 PB0 bidirectional 5 V tolerant LCD/analog-capable GPIO. Alt: TIM1_CH2N, SPI1_NSS, USART3_CK, QUADSPI_BK1_IO1, LCD_SEG5, COMP1_OUT, SAI1_EXTCLK, EVENTOUT. Additional: ADC1_IN15.
27 PB1 bidirectional 5 V tolerant LCD/analog-capable GPIO. Alt: TIM1_CH3N, USART3_RTS_DE, LPUART1_RTS_DE, QUADSPI_BK1_IO0, LCD_SEG6, LPTIM2_IN1, EVENTOUT. Additional: COMP1_INM, ADC1_IN16.
28 PB2 bidirectional 5 V tolerant analog-capable GPIO. Alt: RTC_OUT, LPTIM1_OUT, I2C3_SMBA, LCD_VLCD, EVENTOUT. Additional: COMP1_INP.
29 PB10 bidirectional 5 V tolerant Fm+/LCD GPIO. Alt: TIM2_CH3, I2C2_SCL, SPI2_SCK, USART3_TX, LPUART1_RX, TSC_SYNC, QUADSPI_CLK, LCD_SEG10, COMP1_OUT, SAI1_SCK_A, EVENTOUT.
30 PB11 bidirectional 5 V tolerant Fm+/LCD GPIO. Alt: TIM2_CH4, I2C2_SDA, USART3_RX, LPUART1_TX, QUADSPI_BK1_NCS, LCD_SEG11, COMP2_OUT, EVENTOUT.
31 VSS power_in Digital ground reference.
32 VDD power_in Digital I/O and core regulator supply, 1.71 V to 3.6 V.
33 PB12 bidirectional 5 V tolerant LCD-capable GPIO. Alt: TIM1_BKIN, TIM1_BKIN_COMP2, I2C2_SMBA, SPI2_NSS, USART3_CK, LPUART1_RTS_DE, TSC_G1_IO1, LCD_SEG12, SWPMI1_IO, SAI1_FS_A, TIM15_BKIN, EVENTOUT.
34 PB13 bidirectional 5 V tolerant Fm+/LCD-capable GPIO. Alt: TIM1_CH1N, I2C2_SCL, SPI2_SCK, USART3_CTS, LPUART1_CTS, TSC_G1_IO2, LCD_SEG13, SWPMI1_TX, SAI1_SCK_A, TIM15_CH1N, EVENTOUT.
35 PB14 bidirectional 5 V tolerant Fm+/LCD-capable GPIO. Alt: TIM1_CH2N, I2C2_SDA, SPI2_MISO, USART3_RTS_DE, TSC_G1_IO3, LCD_SEG14, SWPMI1_RX, SAI1_MCLK_A, TIM15_CH1, EVENTOUT.
36 PB15 bidirectional 5 V tolerant LCD-capable GPIO. Alt: RTC_REFIN, TIM1_CH3N, SPI2_MOSI, TSC_G1_IO4, LCD_SEG15, SWPMI1_SUSPEND, SAI1_SD_A, TIM15_CH2, EVENTOUT.
37 PC6 bidirectional 5 V tolerant LCD-capable GPIO. Alt: TSC_G4_IO1, LCD_SEG24, SDMMC1_D6, EVENTOUT.
38 PC7 bidirectional 5 V tolerant LCD-capable GPIO. Alt: TSC_G4_IO2, LCD_SEG25, SDMMC1_D7, EVENTOUT.
39 PC8 bidirectional 5 V tolerant LCD-capable GPIO. Alt: TSC_G4_IO3, LCD_SEG26, SDMMC1_D0, EVENTOUT.
40 PC9 bidirectional 5 V tolerant LCD-capable GPIO. Alt: TSC_G4_IO4, USB_NOE, LCD_SEG27, SDMMC1_D1, EVENTOUT.
41 PA8 bidirectional 5 V tolerant LCD-capable GPIO. Alt: MCO, TIM1_CH1, USART1_CK, LCD_COM0, SWPMI1_IO, SAI1_SCK_A, LPTIM2_OUT, EVENTOUT.
42 PA9 bidirectional 5 V tolerant Fm+/LCD-capable GPIO. Alt: TIM1_CH2, I2C1_SCL, USART1_TX, LCD_COM1, SAI1_FS_A, TIM15_BKIN, EVENTOUT.
43 PA10 bidirectional 5 V tolerant Fm+/LCD-capable GPIO. Alt: TIM1_CH3, I2C1_SDA, USART1_RX, USB_CRS_SYNC, LCD_COM2, SAI1_SD_A, EVENTOUT.
44 PA11 bidirectional 5 V tolerant USB-capable GPIO (FT_u). Alt: TIM1_CH4, TIM1_BKIN2, SPI1_MISO, COMP1_OUT, USART1_CTS, CAN1_RX, USB_DM, TIM1_BKIN2_COMP1, EVENTOUT.
45 PA12 bidirectional 5 V tolerant USB-capable GPIO (FT_u). Alt: TIM1_ETR, SPI1_MOSI, USART1_RTS_DE, CAN1_TX, USB_DP, EVENTOUT.
46 PA13 (JTMS-SWDIO) bidirectional 5 V tolerant GPIO defaulting after reset to SWD/JTAG data (JTMS-SWDIO) with internal pull-up. Alt: JTMS-SWDIO, IR_OUT, USB_NOE, SWPMI1_TX, SAI1_SD_B, EVENTOUT.
47 VSS power_in Digital ground reference.
48 VDDUSB power_in USB transceivers supply, 3.0 V to 3.6 V. Provide a dedicated supply when the USB peripheral is used; can be tied to VDD when both are in the same range.
49 PA14 (JTCK-SWCLK) bidirectional 5 V tolerant GPIO defaulting after reset to SWD/JTAG clock (JTCK-SWCLK) with internal pull-down. Alt: JTCK-SWCLK, LPTIM1_OUT, I2C1_SMBA, SWPMI1_RX, SAI1_FS_B, EVENTOUT.
50 PA15 (JTDI) bidirectional 5 V tolerant LCD-capable GPIO defaulting after reset to JTDI with internal pull-up. Alt: JTDI, TIM2_CH1, TIM2_ETR, USART2_RX, SPI1_NSS, SPI3_NSS, USART3_RTS_DE, TSC_G3_IO1, LCD_SEG17, SWPMI1_SUSPEND, EVENTOUT.
51 PC10 bidirectional 5 V tolerant LCD-capable GPIO. Alt: SPI3_SCK, USART3_TX, TSC_G3_IO2, LCD_COM4/LCD_SEG28/LCD_SEG40, SDMMC1_D2, EVENTOUT.
52 PC11 bidirectional 5 V tolerant LCD-capable GPIO. Alt: SPI3_MISO, USART3_RX, TSC_G3_IO3, LCD_COM5/LCD_SEG29/LCD_SEG41, SDMMC1_D3, EVENTOUT.
53 PC12 bidirectional 5 V tolerant LCD-capable GPIO. Alt: SPI3_MOSI, USART3_CK, TSC_G3_IO4, LCD_COM6/LCD_SEG30/LCD_SEG42, SDMMC1_CK, EVENTOUT.
54 PD2 bidirectional 5 V tolerant LCD-capable GPIO. Alt: USART3_RTS_DE, TSC_SYNC, LCD_COM7/LCD_SEG31/LCD_SEG43, SDMMC1_CMD, EVENTOUT.
55 PB3 (JTDO-TRACESWO) bidirectional 5 V tolerant LCD/analog-capable GPIO defaulting after reset to JTDO/TRACESWO. Alt: JTDO-TRACESWO, TIM2_CH2, SPI1_SCK, SPI3_SCK, USART1_RTS_DE, LCD_SEG7, SAI1_SCK_B, EVENTOUT. Additional: COMP2_INM.
56 PB4 (NJTRST) bidirectional 5 V tolerant Fm+/LCD/analog-capable GPIO defaulting after reset to NJTRST with internal pull-up. Alt: NJTRST, I2C3_SDA, SPI1_MISO, SPI3_MISO, USART1_CTS, TSC_G2_IO1, LCD_SEG8, SAI1_MCLK_B, EVENTOUT. Additional: COMP2_INP.
57 PB5 bidirectional 5 V tolerant LCD-capable GPIO. Alt: LPTIM1_IN1, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI, USART1_CK, TSC_G2_IO2, LCD_SEG9, COMP2_OUT, SAI1_SD_B, TIM16_BKIN, EVENTOUT.
58 PB6 bidirectional 5 V tolerant Fm+/analog-capable GPIO. Alt: LPTIM1_ETR, I2C1_SCL, USART1_TX, TSC_G2_IO3, SAI1_FS_B, TIM16_CH1N, EVENTOUT. Additional: COMP2_INP.
59 PB7 bidirectional 5 V tolerant Fm+/LCD/analog-capable GPIO. Alt: LPTIM1_IN2, I2C1_SDA, USART1_RX, TSC_G2_IO4, LCD_SEG21, EVENTOUT. Additional: COMP2_INM, PVD_IN.
60 PH3-BOOT0 bidirectional GPIO PH3 that is sampled at reset as BOOT0 to select the boot memory (Main Flash / System memory / SRAM). Alt: EVENTOUT.
61 PB8 bidirectional 5 V tolerant Fm+/LCD-capable GPIO. Alt: I2C1_SCL, CAN1_RX, LCD_SEG16, SDMMC1_D4, SAI1_MCLK_A, TIM16_CH1, EVENTOUT.
62 PB9 bidirectional 5 V tolerant Fm+/LCD-capable GPIO. Alt: IR_OUT, I2C1_SDA, SPI2_NSS, CAN1_TX, LCD_COM3, SDMMC1_D5, SAI1_FS_A, EVENTOUT.
63 VSS power_in Digital ground reference.
64 VDD power_in Digital I/O and core regulator supply, 1.71 V to 3.6 V.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-64(10x10)
Category MCU
Pins 64

Ordering variants

  • STM32L433RCT6TR
  • STM32L433RCT6TRRCI6
  • STM32L433RCT6TRRCI6TR
  • STM32L433RCT6TRRCY6
  • STM32L433RCT6TRRCY6TR
  • STM32L433RCT6TRCCT6
  • STM32L433RCT6TRCCT6TR
  • STM32L433RCT6TRCCU6
  • STM32L433RCT6TRCCU6TR
  • STM32L433RCT6TRCCY6
  • STM32L433RCT6TRCCY6TR
  • STM32L433RCT6TRVCT6
  • STM32L433RCT6TRVCT6TR
  • STM32L433RCT6TRVCI6
  • STM32L433RCT6TRVCI6TR

CAD (KiCad official)

  • Symbol: STM32L433RCT6TR
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (None pp, sha256 471e1cceea40b1fa, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

Schematic Symbol

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PCB Footprint

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