STM32H750VBT6 from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PE2	bidirectional	GPIO port E bit 2. 5 V-tolerant FT_h high-speed I/O. Alternate functions: TRACECLK, SAI1_CK1, SPI4_SCK, SAI1_MCLK_A, SAI4_MCLK_A, QUADSPI_BK1_IO2, SAI4_CK1, ETH_MII_TXD3, FMC_A23.
2	PE3	bidirectional	GPIO port E bit 3. FT_h I/O. Alt: TRACED0, TIM15_BKIN, SAI1_SD_B, SAI4_SD_B, FMC_A19.
3	PE4	bidirectional	GPIO port E bit 4. FT_h I/O. Alt: TRACED1, SAI1_D2, DFSDM1_DATIN3, TIM15_CH1N, SPI4_NSS, SAI1_FS_A, FMC_A20, DCMI_D4, LCD_B0.
4	PE5	bidirectional	GPIO port E bit 5. FT_h I/O. Alt: TRACED2, SAI1_CK2, DFSDM1_CKIN3, TIM15_CH1, SPI4_MISO, SAI1_SCK_A, FMC_A21, DCMI_D6, LCD_G0.
5	PE6	bidirectional	GPIO port E bit 6. FT_h I/O. Alt: TRACED3, TIM1_BKIN2, SAI1_D1, TIM15_CH2, SPI4_MOSI, SAI1_SD_A, SAI2_MCLK_B, FMC_A22, DCMI_D7, LCD_G1.
6	VBAT	power_in	Backup battery supply (1.2 V to 3.6 V). Powers the RTC, backup registers and backup SRAM when VDD is off.
7	PC13	bidirectional	GPIO port C bit 13. FT I/O with RTC additional functions: RTC_TAMP1, RTC_TS, WKUP4. Limited drive strength (see datasheet).
8	PC14-OSC32_IN	bidirectional	PC14 / 32.768 kHz LSE oscillator input. Function after reset is OSC32_IN. Configurable as GPIO PC14 (FT I/O).
9	PC15-OSC32_OUT	bidirectional	PC15 / 32.768 kHz LSE oscillator output. Function after reset is OSC32_OUT. Configurable as GPIO PC15 (FT I/O).
10	VSS	power_in	Ground reference (0 V). Common return for VDD digital supply.
11	VDD	power_in	Digital I/O and internal regulator supply (1.62 V to 3.6 V). Decouple with 100 nF per pin plus a 4.7 uF bulk cap.
12	PH0-OSC_IN	bidirectional	PH0 / HSE oscillator input. Function after reset is OSC_IN. Configurable as GPIO PH0 (FT I/O).
13	PH1-OSC_OUT	bidirectional	PH1 / HSE oscillator output. Function after reset is OSC_OUT. Configurable as GPIO PH1 (FT I/O).
14	NRST	bidirectional	Bidirectional device reset input/open-drain output with internal weak pull-up. Active low. External RC to VDD recommended.
15	PC0	bidirectional	GPIO port C bit 0. FT_a I/O with analog option (ADC1/2/3 input IN10).
16	PC1	bidirectional	GPIO port C bit 1. FT_a I/O. ADC1/2/3 input IN11, SAI1_D1, ETH_MDC.
17	PC2_C	bidirectional	GPIO port C bit 2 with direct analog switch. FT_a I/O plus dual-pad direct ADC input (ADC3_INN1/INP0).
18	PC3_C	bidirectional	GPIO port C bit 3 with direct analog switch. FT_a I/O plus dual-pad direct ADC input (ADC3_INP1).
19	VSSA	power_in	Analog ground reference. Connect to VSS at a single point near the ADC reference decoupling.
20	VREF+	power_in	Positive reference voltage for ADC and DAC (1.62 V to VDDA). Decouple with 100 nF + 1 uF to VSSA.
21	VDDA	power_in	Analog supply for ADC, DAC, comparators and reset block (1.62 V to 3.6 V). Must be within specified delta of VDD.
22	PA0	bidirectional	GPIO port A bit 0. FT_a I/O. Alt: TIM2_CH1/ETR, TIM5_CH1, TIM8_ETR, USART2_CTS, UART4_TX, SDMMC2_CMD, ETH_MII_CRS. Analog: ADC1_INP16 / WKUP1.
23	PA1	bidirectional	GPIO port A bit 1. FT_a I/O. Alt: TIM2_CH2, TIM5_CH2, USART2_RTS, UART4_RX, ETH_MII_RX_CLK/RMII_REF_CLK. Analog: ADC1_INP17.
24	PA2	bidirectional	GPIO port A bit 2. FT_a I/O. Alt: TIM2_CH3, TIM5_CH3, TIM15_CH1, USART2_TX, ETH_MDIO, LCD_R1. Analog: ADC1_INP14.
25	PA3	bidirectional	GPIO port A bit 3. FT_a I/O. Alt: TIM2_CH4, TIM5_CH4, TIM15_CH2, USART2_RX, LCD_B2, LCD_B5. Analog: ADC1_INP15.
26	VSS	power_in	Ground reference (0 V).
27	VDD	power_in	Digital I/O and internal regulator supply (1.62 V to 3.6 V).
28	PA4	bidirectional	GPIO port A bit 4. FT_a I/O. Alt: SPI1_NSS, SPI3_NSS, USART2_CK, DCMI_HSYNC, LCD_VSYNC. Analog: DAC1_OUT1, ADC12_INP18.
29	PA5	bidirectional	GPIO port A bit 5. FT_a I/O. Alt: TIM2_CH1/ETR, TIM8_CH1N, SPI1_SCK. Analog: DAC1_OUT2, ADC12_INP19.
30	PA6	bidirectional	GPIO port A bit 6. FT_a I/O. Alt: TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO, TIM13_CH1, DCMI_PIXCLK, LCD_G2. Analog: ADC12_INP3.
31	PA7	bidirectional	GPIO port A bit 7. FT_a I/O. Alt: TIM1_CH1N, TIM3_CH2, TIM8_CH1N, SPI1_MOSI, TIM14_CH1, ETH_MII_RX_DV/RMII_CRS_DV. Analog: ADC12_INP7.
32	PC4	bidirectional	GPIO port C bit 4. FT_a I/O. Alt: SPDIFRX_IN2, I2S1_MCK, ETH_MII_RXD0/RMII_RXD0. Analog: ADC12_INP4.
33	PC5	bidirectional	GPIO port C bit 5. FT_a I/O. Alt: SAI1_D3, SPDIFRX_IN3, ETH_MII_RXD1/RMII_RXD1. Analog: ADC12_INP8.
34	PB0	bidirectional	GPIO port B bit 0. FT_a I/O. Alt: TIM1_CH2N, TIM3_CH3, TIM8_CH2N, UART4_CTS, LCD_R3, ETH_MII_RXD2. Analog: ADC12_INP9.
35	PB1	bidirectional	GPIO port B bit 1. FT_a I/O. Alt: TIM1_CH3N, TIM3_CH4, TIM8_CH3N, LCD_R6, ETH_MII_RXD3. Analog: ADC12_INP5.
36	PB2	bidirectional	GPIO port B bit 2. FT_h I/O. Alt: SAI1_D1, ETH_TX_ER, QUADSPI_CLK, SAI4_D1, SAI1_SD_A, RTC_OUT2.
37	PE7	bidirectional	GPIO port E bit 7. FT_h I/O. Alt: TIM1_ETR, UART7_RX, QUADSPI_BK2_IO0, FMC_D4, LCD_B6.
38	PE8	bidirectional	GPIO port E bit 8. FT_h I/O. Alt: TIM1_CH1N, UART7_TX, QUADSPI_BK2_IO1, FMC_D5, LCD_B7.
39	PE9	bidirectional	GPIO port E bit 9. FT_h I/O. Alt: TIM1_CH1, UART7_RTS, QUADSPI_BK2_IO2, FMC_D6.
40	PE10	bidirectional	GPIO port E bit 10. FT_h I/O. Alt: TIM1_CH2N, UART7_CTS, QUADSPI_BK2_IO3, FMC_D7.
41	PE11	bidirectional	GPIO port E bit 11. FT_h I/O. Alt: TIM1_CH2, SPI4_NSS, FMC_D8, LCD_G3.
42	PE12	bidirectional	GPIO port E bit 12. FT_h I/O. Alt: TIM1_CH3N, SPI4_SCK, FMC_D9, LCD_B4.
43	PE13	bidirectional	GPIO port E bit 13. FT_h I/O. Alt: TIM1_CH3, SPI4_MISO, FMC_D10, LCD_DE.
44	PE14	bidirectional	GPIO port E bit 14. FT_h I/O. Alt: TIM1_CH4, SPI4_MOSI, FMC_D11, LCD_CLK.
45	PE15	bidirectional	GPIO port E bit 15. FT_h I/O. Alt: TIM1_BKIN, FMC_D12, LCD_R7.
46	PB10	bidirectional	GPIO port B bit 10. FT_hf I/O. Alt: TIM2_CH3, I2C2_SCL, SPI2_SCK/I2S2_CK, USART3_TX, LCD_G4, ETH_MII_RX_ER.
47	PB11	bidirectional	GPIO port B bit 11. FT_hf I/O. Alt: TIM2_CH4, I2C2_SDA, USART3_RX, ETH_MII_TX_EN/RMII_TX_EN, LCD_G5.
48	VCAP	power_out	Internal core LDO regulator output. Requires external 2.2 uF low-ESR ceramic capacitor to VSS. Do not connect to any external load.
49	VSS	power_in	Ground reference (0 V).
50	VDD	power_in	Digital I/O and internal regulator supply (1.62 V to 3.6 V).
51	PB12	bidirectional	GPIO port B bit 12. FT_h I/O. Alt: TIM1_BKIN, I2C2_SMBA, SPI2_NSS/I2S2_WS, USART3_CK, CAN2_RX, OTG_HS_ULPI_D5, ETH_MII_TXD0/RMII_TXD0.
52	PB13	bidirectional	GPIO port B bit 13. FT_h I/O. Alt: TIM1_CH1N, SPI2_SCK/I2S2_CK, USART3_CTS, CAN2_TX, OTG_HS_ULPI_D6, ETH_MII_TXD1/RMII_TXD1.
53	PB14	bidirectional	GPIO port B bit 14. FT_hu I/O. Alt: TIM1_CH2N, TIM8_CH2N, USART1_TX, SPI2_MISO/I2S2_SDI, TIM12_CH1, SDMMC2_D0, OTG_HS_DM.
54	PB15	bidirectional	GPIO port B bit 15. FT_hu I/O. Alt: RTC_REFIN, TIM1_CH3N, TIM8_CH3N, USART1_RX, SPI2_MOSI/I2S2_SDO, TIM12_CH2, SDMMC2_D1, OTG_HS_DP.
55	PD8	bidirectional	GPIO port D bit 8. FT_h I/O. Alt: SAI3_SCK_A, SPDIFRX_IN1, USART3_TX, FMC_D13, LCD_R2.
56	PD9	bidirectional	GPIO port D bit 9. FT_h I/O. Alt: SAI3_SD_A, USART3_RX, FMC_D14.
57	PD10	bidirectional	GPIO port D bit 10. FT_h I/O. Alt: SAI3_FS_A, USART3_CK, FMC_D15, LCD_B3.
58	PD11	bidirectional	GPIO port D bit 11. FT_h I/O. Alt: I2C4_SMBA, USART3_CTS, QUADSPI_BK1_IO0, SAI2_SD_A, FMC_A16, FMC_CLE.
59	PD12	bidirectional	GPIO port D bit 12. FT_h I/O. Alt: TIM4_CH1, LPTIM1_IN1, I2C4_SCL, USART3_RTS, QUADSPI_BK1_IO1, SAI2_FS_A, FMC_A17, FMC_ALE.
60	PD13	bidirectional	GPIO port D bit 13. FT_h I/O. Alt: TIM4_CH2, LPTIM1_OUT, I2C4_SDA, QUADSPI_BK1_IO3, SAI2_SCK_A, FMC_A18.
61	PD14	bidirectional	GPIO port D bit 14. FT_h I/O. Alt: TIM4_CH3, UART8_CTS, FMC_D0.
62	PD15	bidirectional	GPIO port D bit 15. FT_h I/O. Alt: TIM4_CH4, UART8_RTS, FMC_D1.
63	PC6	bidirectional	GPIO port C bit 6. FT_h I/O. Alt: TIM3_CH1, TIM8_CH1, I2S2_MCK, USART6_TX, DFSDM1_CKIN3, FMC_NWAIT, SDMMC1_D0DIR, LCD_HSYNC, DCMI_D0.
64	PC7	bidirectional	GPIO port C bit 7. FT_h I/O. Alt: TIM3_CH2, TIM8_CH2, I2S3_MCK, USART6_RX, DFSDM1_DATIN3, SWPMI1_TX, SDMMC1_D123DIR, LCD_G6, DCMI_D1.
65	PC8	bidirectional	GPIO port C bit 8. FT_h I/O. Alt: TIM3_CH3, TIM8_CH3, USART6_CK, UART5_RTS, TRACED1, SDMMC1_D0, DCMI_D2.
66	PC9	bidirectional	GPIO port C bit 9. FT_h I/O. Alt: MCO2, TIM3_CH4, TIM8_CH4, I2C3_SDA, I2S_CKIN, UART5_CTS, QUADSPI_BK1_IO0, SDMMC1_D1, DCMI_D3, LCD_B2.
67	PA8	bidirectional	GPIO port A bit 8. FT_h I/O. Alt: MCO1, TIM1_CH1, TIM8_BKIN2, I2C3_SCL, USART1_CK, HRTIM1_CHA1/CHA2, OTG_FS_SOF, LCD_R6.
68	PA9	bidirectional	GPIO port A bit 9. FT_h I/O. Alt: TIM1_CH2, I2C3_SMBA, SPI2_SCK/I2S2_CK, USART1_TX, DCMI_D0, LCD_R5. Also VBUS_FS sensing.
69	PA10	bidirectional	GPIO port A bit 10. FT_hu I/O. Alt: TIM1_CH3, USART1_RX, DCMI_D1, OTG_FS_ID, MDIOS_MDIO, LCD_B1.
70	PA11	bidirectional	GPIO port A bit 11. FT_hu I/O. Alt: TIM1_CH4, USART1_CTS, CAN1_RX, UART4_RX, LCD_R4. USB OTG_FS_DM.
71	PA12	bidirectional	GPIO port A bit 12. FT_hu I/O. Alt: TIM1_ETR, USART1_RTS, CAN1_TX, UART4_TX, LCD_R5. USB OTG_FS_DP.
72	PA13	bidirectional	GPIO port A bit 13. FT I/O. Function after reset: JTMS-SWDIO (SWD data / JTAG mode select) with internal pull-up. Alt: TRACESWO.
73	VCAP	power_out	Second internal core LDO decoupling pin. Requires external 2.2 uF low-ESR ceramic capacitor to VSS.
74	VSS	power_in	Ground reference (0 V).
75	VDD	power_in	Digital I/O and internal regulator supply (1.62 V to 3.6 V).
76	PA14	bidirectional	GPIO port A bit 14. FT I/O. Function after reset: JTCK-SWCLK (SWD/JTAG clock) with internal pull-down.
77	PA15	bidirectional	GPIO port A bit 15. FT I/O. Function after reset: JTDI (JTAG data-in) with internal pull-up. Alt: TIM2_CH1/ETR, HDMI_CEC, SPI1_NSS, SPI3_NSS/I2S3_WS, UART4_RTS, UART7_TX.
78	PC10	bidirectional	GPIO port C bit 10. FT_h I/O. Alt: SPI3_SCK/I2S3_CK, USART3_TX, UART4_TX, QUADSPI_BK1_IO1, SDMMC1_D2, DCMI_D8, LCD_R2.
79	PC11	bidirectional	GPIO port C bit 11. FT_h I/O. Alt: SPI3_MISO, USART3_RX, UART4_RX, QUADSPI_BK2_NCS, SDMMC1_D3, DCMI_D4.
80	PC12	bidirectional	GPIO port C bit 12. FT_h I/O. Alt: MCO2 (backup), SPI3_MOSI/I2S3_SDO, USART3_CK, UART5_TX, SDMMC1_CK, DCMI_D9.
81	PB3	bidirectional	GPIO port B bit 3. FT_h I/O. Function after reset: JTDO/TRACESWO. Alt: TIM2_CH2, SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, USART1_RX.
82	PB4	bidirectional	GPIO port B bit 4. FT_h I/O. Function after reset: NJTRST (JTAG reset) with pull-up. Alt: TIM3_CH1, TIM16_BKIN, SPI1_MISO/I2S1_SDI, SPI3_MISO, SDMMC2_D3.
83	PB5	bidirectional	GPIO port B bit 5. FT_h I/O. Alt: TIM3_CH2, TIM17_BKIN, I2C1_SMBA, SPI1_MOSI/I2S1_SDO, SPI3_MOSI/I2S3_SDO, CAN2_RX, OTG_HS_ULPI_D7, ETH_PPS_OUT.
84	PB6	bidirectional	GPIO port B bit 6. FT_hf I/O. Alt: TIM4_CH1, TIM16_CH1N, HDMI_CEC, I2C1_SCL, I2C4_SCL, USART1_TX, CAN2_TX, QUADSPI_BK1_NCS, DFSDM1_DATIN5.
85	PB7	bidirectional	GPIO port B bit 7. FT_hf I/O. Alt: TIM4_CH2, TIM17_CH1N, I2C1_SDA, I2C4_SDA, USART1_RX, FMC_NL, DFSDM1_CKIN5, DCMI_VSYNC.
86	BOOT0	input	Boot mode selection input. Sampled at reset to choose between user flash, system bootloader and SRAM. Dedicated pin (B type) with internal pull-down; drive high through 10 kΩ to enter bootloader.
87	PB8	bidirectional	GPIO port B bit 8. FT_hf I/O. Alt: TIM4_CH3, TIM16_CH1, HDMI_CEC, I2C1_SCL, I2C4_SCL, UART4_RX, CAN1_RX, SDMMC1_D4, DCMI_D6, LCD_B6, ETH_MII_TXD3.
88	PB9	bidirectional	GPIO port B bit 9. FT_hf I/O. Alt: TIM4_CH4, TIM17_CH1, I2C1_SDA, I2C4_SDA, SPI2_NSS/I2S2_WS, UART4_TX, CAN1_TX, SDMMC1_CDIR, SDMMC2_D5, LCD_B7.
89	PE0	bidirectional	GPIO port E bit 0. FT_h I/O. Alt: TIM4_ETR, LPTIM1_IN1, UART8_RX, SAI2_MCLK_A, FMC_NBL0, DCMI_D2, LCD_R0.
90	PE1	bidirectional	GPIO port E bit 1. FT_h I/O. Alt: LPTIM1_OUT, UART8_TX, FMC_NBL1, LCD_R6.
91	PD0	bidirectional	GPIO port D bit 0. FT_h I/O. Alt: CAN1_RX, UART4_RX, FMC_D2.
92	PD1	bidirectional	GPIO port D bit 1. FT_h I/O. Alt: CAN1_TX, UART4_TX, FMC_D3.
93	PD2	bidirectional	GPIO port D bit 2. FT_h I/O. Alt: TIM3_ETR, UART5_RX, TRACED2, SDMMC1_CMD, DCMI_D11.
94	PD3	bidirectional	GPIO port D bit 3. FT_h I/O. Alt: SPI2_SCK/I2S2_CK, USART2_CTS, FMC_CLK, DCMI_D5, LCD_G7.
95	PD4	bidirectional	GPIO port D bit 4. FT_h I/O. Alt: USART2_RTS, FMC_NOE.
96	PD5	bidirectional	GPIO port D bit 5. FT_h I/O. Alt: USART2_TX, FMC_NWE.
97	PD6	bidirectional	GPIO port D bit 6. FT_h I/O. Alt: SAI1_D1, SPI3_MOSI/I2S3_SDO, SDMMC2_CK, USART2_RX, FMC_NWAIT, DCMI_D10, LCD_B2.
98	PD7	bidirectional	GPIO port D bit 7. FT_h I/O. Alt: SAI1_SD_A, SPI1_MOSI/I2S1_SDO, USART2_CK, SPDIFRX_IN0, FMC_NE1.
99	VSS	power_in	Ground reference (0 V).
100	VDD	power_in	Digital I/O and internal regulator supply (1.62 V to 3.6 V).

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	LQFP-100(14x14)
Category	MCU
Pins	100

Ordering variants

Same part, different packaging or reel option.

STM32H750VBT6
STM32H750VBT6TR
STM32H750VBT6ZBT6
STM32H750VBT6ZBT6TR
STM32H750VBT6IBT6
STM32H750VBT6IBT6TR
STM32H750VBT6IBK6
STM32H750VBT6XBH6

CAD (KiCad official)

Symbol: STM32H750VBT6
Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
3D model: LQFP-100(14x14) (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`stm32h750vbt6.step`	1305 KB	You want the bare part, or you mark your own boards.
`stm32h750vbt6-etched.step`	7.4 MB	You want the part with `STM32H750VBT6` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 1839 faces against 1535 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (337 pp, sha256 42ade68c8352948d, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF