STM32F401RET6 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VBAT	power_in	Backup domain supply, 1.65 V to 3.6 V. Powers the RTC, LSE oscillator and backup registers when VDD is off.
2	PC13	bidirectional	GPIO Port C bit 13. Supplied through the power switch (limited drive: ≤2 MHz, ≤30 pF, no LED). Additional functions: RTC_TAMP1, RTC_OUT, RTC_TS. Alternate: EVENTOUT.
3	PC14-OSC32_IN	bidirectional	GPIO PC14 / LSE 32.768 kHz oscillator input. Backup-domain I/O supplied through the power switch (limited drive). FT except in analog/oscillator mode.
4	PC15-OSC32_OUT	bidirectional	GPIO PC15 / LSE 32.768 kHz oscillator output. Backup-domain I/O supplied through the power switch (limited drive). FT except in analog/oscillator mode.
5	PH0-OSC_IN	bidirectional	GPIO PH0 / HSE 4-26 MHz main oscillator input. FT except in analog/oscillator mode.
6	PH1-OSC_OUT	bidirectional	GPIO PH1 / HSE main oscillator output. FT except in analog/oscillator mode.
7	NRST	bidirectional	Bidirectional device reset pin (active low) with embedded weak pull-up (~40 kΩ). Drive low to force a system reset; the MCU also drives it low internally during an internal reset event.
8	PC0	bidirectional	GPIO Port C bit 0, 5 V tolerant. Additional analog function: ADC1_IN10. Alternate: EVENTOUT.
9	PC1	bidirectional	GPIO Port C bit 1, 5 V tolerant. Additional analog function: ADC1_IN11. Alternate: EVENTOUT.
10	PC2	bidirectional	GPIO Port C bit 2, 5 V tolerant. Additional analog function: ADC1_IN12. Alternates: SPI2_MISO, I2S2ext_SD, EVENTOUT.
11	PC3	bidirectional	GPIO Port C bit 3, 5 V tolerant. Additional analog function: ADC1_IN13. Alternates: SPI2_MOSI/I2S2_SD, EVENTOUT.
12	VSSA/VREF-	power_in	Analog ground and negative ADC reference (tied together in LQFP64). Connect to the board analog ground.
13	VDDA/VREF+	power_in	Analog supply and positive ADC reference (tied together in LQFP64). 1.7 V (min) to 3.6 V; must be ≥ VDD when both are powered.
14	PA0	bidirectional	GPIO Port A bit 0, 5 V tolerant. Additional functions: ADC1_IN0, WKUP. Alternates: USART2_CTS, TIM2_CH1/TIM2_ETR, TIM5_CH1, EVENTOUT.
15	PA1	bidirectional	GPIO Port A bit 1, 5 V tolerant. Additional function: ADC1_IN1. Alternates: USART2_RTS, TIM2_CH2, TIM5_CH2, EVENTOUT.
16	PA2	bidirectional	GPIO Port A bit 2, 5 V tolerant. Additional function: ADC1_IN2. Alternates: USART2_TX, TIM2_CH3, TIM5_CH3, TIM9_CH1, EVENTOUT.
17	PA3	bidirectional	GPIO Port A bit 3, 5 V tolerant. Additional function: ADC1_IN3. Alternates: USART2_RX, TIM2_CH4, TIM5_CH4, TIM9_CH2, EVENTOUT.
18	VSS	power_in	Digital ground reference for VDD supply domain.
19	VDD	power_in	Digital supply, 1.7 V to 3.6 V. Decouple with 100 nF close to each VDD pin plus one bulk 4.7 µF.
20	PA4	bidirectional	GPIO Port A bit 4, 5 V tolerant. Additional function: ADC1_IN4. Alternates: SPI1_NSS, SPI3_NSS/I2S3_WS, USART2_CK, EVENTOUT.
21	PA5	bidirectional	GPIO Port A bit 5, 5 V tolerant. Additional function: ADC1_IN5. Alternates: SPI1_SCK, TIM2_CH1/TIM2_ETR, EVENTOUT.
22	PA6	bidirectional	GPIO Port A bit 6, 5 V tolerant. Additional function: ADC1_IN6. Alternates: SPI1_MISO, TIM1_BKIN, TIM3_CH1, EVENTOUT.
23	PA7	bidirectional	GPIO Port A bit 7, 5 V tolerant. Additional function: ADC1_IN7. Alternates: SPI1_MOSI, TIM1_CH1N, TIM3_CH2, EVENTOUT.
24	PC4	bidirectional	GPIO Port C bit 4, 5 V tolerant. Additional function: ADC1_IN14. Alternate: EVENTOUT.
25	PC5	bidirectional	GPIO Port C bit 5, 5 V tolerant. Additional function: ADC1_IN15. Alternate: EVENTOUT.
26	PB0	bidirectional	GPIO Port B bit 0, 5 V tolerant. Additional function: ADC1_IN8. Alternates: TIM1_CH2N, TIM3_CH3, EVENTOUT.
27	PB1	bidirectional	GPIO Port B bit 1, 5 V tolerant. Additional function: ADC1_IN9. Alternates: TIM1_CH3N, TIM3_CH4, EVENTOUT.
28	PB2	bidirectional	GPIO Port B bit 2, 5 V tolerant. Additional function: BOOT1 (sampled at reset with BOOT0 to select boot memory). Alternate: EVENTOUT.
29	PB10	bidirectional	GPIO Port B bit 10, 5 V tolerant. Alternates: SPI2_SCK/I2S2_CK, I2C2_SCL, TIM2_CH3, EVENTOUT.
30	VCAP1	passive	Internal 1.2 V core-regulator decoupling. Connect a 2.2 µF (typical) low-ESR ceramic capacitor to VSS. Do NOT drive externally when the internal regulator is enabled.
31	VSS	power_in	Digital ground reference for VDD supply domain.
32	VDD	power_in	Digital supply, 1.7 V to 3.6 V. Decouple with 100 nF close to each VDD pin plus one bulk 4.7 µF.
33	PB12	bidirectional	GPIO Port B bit 12, 5 V tolerant. Alternates: SPI2_NSS/I2S2_WS, I2C2_SMBA, TIM1_BKIN, EVENTOUT.
34	PB13	bidirectional	GPIO Port B bit 13, 5 V tolerant. Alternates: SPI2_SCK/I2S2_CK, TIM1_CH1N, EVENTOUT.
35	PB14	bidirectional	GPIO Port B bit 14, 5 V tolerant. Alternates: SPI2_MISO, I2S2ext_SD, TIM1_CH2N, EVENTOUT.
36	PB15	bidirectional	GPIO Port B bit 15, 5 V tolerant. Additional function: RTC_REFIN. Alternates: SPI2_MOSI/I2S2_SD, TIM1_CH3N, EVENTOUT.
37	PC6	bidirectional	GPIO Port C bit 6, 5 V tolerant. Alternates: I2S2_MCK, USART6_TX, TIM3_CH1, SDIO_D6, EVENTOUT.
38	PC7	bidirectional	GPIO Port C bit 7, 5 V tolerant. Alternates: I2S3_MCK, USART6_RX, TIM3_CH2, SDIO_D7, EVENTOUT.
39	PC8	bidirectional	GPIO Port C bit 8, 5 V tolerant. Alternates: USART6_CK, TIM3_CH3, SDIO_D0, EVENTOUT.
40	PC9	bidirectional	GPIO Port C bit 9, 5 V tolerant. Alternates: I2S_CKIN, I2C3_SDA, TIM3_CH4, SDIO_D1, MCO_2, EVENTOUT.
41	PA8	bidirectional	GPIO Port A bit 8, 5 V tolerant. Alternates: I2C3_SCL, USART1_CK, TIM1_CH1, OTG_FS_SOF, MCO_1, EVENTOUT.
42	PA9	bidirectional	GPIO Port A bit 9, 5 V tolerant. Additional function: OTG_FS_VBUS. Alternates: I2C3_SMBA, USART1_TX, TIM1_CH2, EVENTOUT.
43	PA10	bidirectional	GPIO Port A bit 10, 5 V tolerant. Alternates: USART1_RX, TIM1_CH3, OTG_FS_ID, EVENTOUT.
44	PA11	bidirectional	GPIO Port A bit 11, 5 V tolerant. Alternates: USART1_CTS, USART6_TX, TIM1_CH4, OTG_FS_DM, EVENTOUT.
45	PA12	bidirectional	GPIO Port A bit 12, 5 V tolerant. Alternates: USART1_RTS, USART6_RX, TIM1_ETR, OTG_FS_DP, EVENTOUT.
46	PA13 (JTMS-SWDIO)	bidirectional	GPIO PA13, default function JTMS-SWDIO after reset (SWD data / JTAG mode select). 5 V tolerant. Alternate: EVENTOUT.
47	VSS	power_in	Digital ground reference for VDD supply domain.
48	VDD	power_in	Digital supply, 1.7 V to 3.6 V. Decouple with 100 nF close to each VDD pin plus one bulk 4.7 µF.
49	PA14 (JTCK-SWCLK)	bidirectional	GPIO PA14, default function JTCK-SWCLK after reset (SWD/JTAG clock). 5 V tolerant. Alternate: EVENTOUT.
50	PA15 (JTDI)	bidirectional	GPIO PA15, default function JTDI after reset (JTAG data in). 5 V tolerant. Alternates: SPI1_NSS, SPI3_NSS/I2S3_WS, TIM2_CH1/TIM2_ETR, EVENTOUT.
51	PC10	bidirectional	GPIO Port C bit 10, 5 V tolerant. Alternates: SPI3_SCK/I2S3_CK, SDIO_D2, EVENTOUT.
52	PC11	bidirectional	GPIO Port C bit 11, 5 V tolerant. Alternates: I2S3ext_SD, SPI3_MISO, SDIO_D3, EVENTOUT.
53	PC12	bidirectional	GPIO Port C bit 12, 5 V tolerant. Alternates: SPI3_MOSI/I2S3_SD, SDIO_CK, EVENTOUT.
54	PD2	bidirectional	GPIO Port D bit 2, 5 V tolerant. Alternates: TIM3_ETR, SDIO_CMD, EVENTOUT.
55	PB3 (JTDO-SWO)	bidirectional	GPIO PB3, default function JTDO/traceSWO after reset. 5 V tolerant. Alternates: SPI1_SCK, SPI3_SCK/I2S3_CK, I2C2_SDA, TIM2_CH2, EVENTOUT.
56	PB4 (NJTRST)	bidirectional	GPIO PB4, default function NJTRST after reset (JTAG reset, active low). 5 V tolerant. Alternates: SPI1_MISO, SPI3_MISO, I2S3ext_SD, I2C3_SDA, TIM3_CH1, EVENTOUT.
57	PB5	bidirectional	GPIO Port B bit 5, 5 V tolerant. Alternates: SPI1_MOSI, SPI3_MOSI/I2S3_SD, I2C1_SMBA, TIM3_CH2, EVENTOUT.
58	PB6	bidirectional	GPIO Port B bit 6, 5 V tolerant. Alternates: I2C1_SCL, USART1_TX, TIM4_CH1, EVENTOUT.
59	PB7	bidirectional	GPIO Port B bit 7, 5 V tolerant. Alternates: I2C1_SDA, USART1_RX, TIM4_CH2, EVENTOUT.
60	BOOT0	input	Dedicated boot-mode select input, sampled at reset. Combined with BOOT1 (PB2) it selects boot from main Flash (BOOT0=0), system memory bootloader (BOOT0=1,BOOT1=0), or embedded SRAM (BOOT0=1,BOOT1=1). Also serves as V_PP for factory programming.
61	PB8	bidirectional	GPIO Port B bit 8, 5 V tolerant. Alternates: I2C1_SCL, TIM4_CH3, TIM10_CH1, SDIO_D4, EVENTOUT.
62	PB9	bidirectional	GPIO Port B bit 9, 5 V tolerant. Alternates: SPI2_NSS/I2S2_WS, I2C1_SDA, TIM4_CH4, TIM11_CH1, SDIO_D5, EVENTOUT.
63	VSS	power_in	Digital ground reference for VDD supply domain.
64	VDD	power_in	Digital supply, 1.7 V to 3.6 V. Decouple with 100 nF close to each VDD pin plus one bulk 4.7 µF.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	LQFP-64(10x10)
Category	MCU
Pins	64

Ordering variants

Same part, different packaging or reel option.

STM32F401RDT6
STM32F401RET6
STM32F401CDY
STM32F401CEY
STM32F401CDU
STM32F401CEU
STM32F401VDT6
STM32F401VET6
STM32F401VDH6
STM32F401VEH6

CAD (KiCad official)

Symbol: STM32F401RET6
Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
3D model: LQFP-64(10x10) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (135 pp, sha256 7daad2163948dcbe, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF