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stm32f105rct6

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by Ray

STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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STM32F105RCT6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

STM32F105RCT6 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup domain supply, 1.8-3.6 V. Powers RTC, LSE oscillator and backup registers when VDD is off; tie to VDD if unused.
2 PC13-TAMPER-RTC bidirectional GPIO PC13 shared with RTC tamper input / RTC alarm/second output. Supplied through the backup power switch - output mode limited to 2 MHz, 30 pF, one PC13/14/15 pin driving at a time.
3 PC14-OSC32_IN bidirectional GPIO PC14 shared with 32.768 kHz LSE crystal input. Same backup-domain drive restrictions as PC13. Connect to LSE crystal when RTC crystal is used.
4 PC15-OSC32_OUT bidirectional GPIO PC15 shared with 32.768 kHz LSE crystal output. Same backup-domain drive restrictions as PC13. Connect to LSE crystal when RTC crystal is used.
5 OSC_IN input HSE 3-25 MHz crystal input (or external clock input). On LQFP64, pins 5/6 default to OSC_IN/OSC_OUT after reset and can be remapped by software to PD0/PD1.
6 OSC_OUT output HSE crystal output. On LQFP64, software-remappable to PD1.
7 NRST bidirectional Bidirectional device reset, active low. Internal weak pull-up; can be driven low externally or by internal reset sources.
8 PC0 bidirectional GPIO PC0 / ADC12_IN10 (ADC1 and ADC2 channel 10).
9 PC1 bidirectional GPIO PC1 / ADC12_IN11 / ETH_MII_MDC / ETH_RMII_MDC. Ethernet MDIO clock in MII/RMII modes.
10 PC2 bidirectional GPIO PC2 / ADC12_IN12 / ETH_MII_TXD2.
11 PC3 bidirectional GPIO PC3 / ADC12_IN13 / ETH_MII_TX_CLK.
12 VSSA power_in Analog ground reference for ADC, DAC, VREF and analog power domain. Tie to system ground plane; decouple VDDA/VREF with 10 nF + 1 µF to VSSA.
13 VDDA power_in Analog supply, 2.0-3.6 V (2.4-3.6 V when the ADC is used). Powers ADC, DAC, reset, PLL and internal reference; keep within 300 mV of VDD.
14 PA0-WKUP bidirectional GPIO PA0 / wake-up input from Standby. Alternate functions: WKUP, USART2_CTS, ADC12_IN0, TIM2_CH1_ETR, TIM5_CH1, ETH_MII_CRS_WKUP.
15 PA1 bidirectional GPIO PA1. Alt: USART2_RTS, ADC12_IN1, TIM5_CH2, TIM2_CH2, ETH_MII_RX_CLK, ETH_RMII_REF_CLK.
16 PA2 bidirectional GPIO PA2. Alt: USART2_TX, TIM5_CH3, ADC12_IN2, TIM2_CH3, ETH_MII_MDIO, ETH_RMII_MDIO.
17 PA3 bidirectional GPIO PA3. Alt: USART2_RX, TIM5_CH4, ADC12_IN3, TIM2_CH4, ETH_MII_COL.
18 VSS_4 power_in Digital ground. Tie to common system ground.
19 VDD_4 power_in Digital supply, 2.0-3.6 V. One of five VDD pins; each requires a local 100 nF decoupling capacitor, plus one 4.7 µF on VDD3.
20 PA4 bidirectional GPIO PA4. Alt: SPI1_NSS, DAC_OUT1, USART2_CK, ADC12_IN4; remap SPI3_NSS / I2S3_WS.
21 PA5 bidirectional GPIO PA5. Alt: SPI1_SCK, DAC_OUT2, ADC12_IN5.
22 PA6 bidirectional GPIO PA6. Alt: SPI1_MISO, ADC12_IN6, TIM3_CH1; remap TIM1_BKIN.
23 PA7 bidirectional GPIO PA7. Alt: SPI1_MOSI, ADC12_IN7, TIM3_CH2, ETH_MII_RX_DV, ETH_RMII_CRS_DV; remap TIM1_CH1N.
24 PC4 bidirectional GPIO PC4. Alt: ADC12_IN14, ETH_MII_RXD0, ETH_RMII_RXD0.
25 PC5 bidirectional GPIO PC5. Alt: ADC12_IN15, ETH_MII_RXD1, ETH_RMII_RXD1.
26 PB0 bidirectional GPIO PB0. Alt: ADC12_IN8, TIM3_CH3, ETH_MII_RXD2; remap TIM1_CH2N.
27 PB1 bidirectional GPIO PB1. Alt: ADC12_IN9, TIM3_CH4, ETH_MII_RXD3; remap TIM1_CH3N.
28 PB2/BOOT1 bidirectional GPIO PB2, also sampled at reset as BOOT1 to help select the boot source together with BOOT0. 5 V tolerant.
29 PB10 bidirectional GPIO PB10. Alt: I2C2_SCL, USART3_TX, ETH_MII_RX_ER; remap TIM2_CH3.
30 PB11 bidirectional GPIO PB11. Alt: I2C2_SDA, USART3_RX, ETH_MII_TX_EN, ETH_RMII_TX_EN; remap TIM2_CH4.
31 VSS_1 power_in Digital ground. Tie to common system ground.
32 VDD_1 power_in Digital supply, 2.0-3.6 V. Decouple with 100 nF to nearest VSS.
33 PB12 bidirectional GPIO PB12. Alt: SPI2_NSS, I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN, CAN2_RX, ETH_MII_TXD0, ETH_RMII_TXD0.
34 PB13 bidirectional GPIO PB13. Alt: SPI2_SCK, I2S2_CK, USART3_CTS, TIM1_CH1N, CAN2_TX, ETH_MII_TXD1, ETH_RMII_TXD1.
35 PB14 bidirectional GPIO PB14. Alt: SPI2_MISO, TIM1_CH2N, USART3_RTS.
36 PB15 bidirectional GPIO PB15. Alt: SPI2_MOSI, I2S2_SD, TIM1_CH3N.
37 PC6 bidirectional GPIO PC6. Alt: I2S2_MCK; remap TIM3_CH1.
38 PC7 bidirectional GPIO PC7. Alt: I2S3_MCK; remap TIM3_CH2.
39 PC8 bidirectional GPIO PC8. Remap: TIM3_CH3.
40 PC9 bidirectional GPIO PC9. Remap: TIM3_CH4.
41 PA8 bidirectional GPIO PA8. Alt: USART1_CK, OTG_FS_SOF, TIM1_CH1, MCO (microcontroller clock output).
42 PA9 bidirectional GPIO PA9. Alt: USART1_TX, TIM1_CH2, OTG_FS_VBUS (USB VBUS sense input).
43 PA10 bidirectional GPIO PA10. Alt: USART1_RX, TIM1_CH3, OTG_FS_ID.
44 PA11 bidirectional GPIO PA11. Alt: USART1_CTS, CAN1_RX, TIM1_CH4, OTG_FS_DM (USB D-).
45 PA12 bidirectional GPIO PA12. Alt: USART1_RTS, OTG_FS_DP (USB D+), CAN1_TX, TIM1_ETR.
46 PA13 bidirectional After reset: JTMS / SWDIO (SWD data). Remappable to PA13 GPIO once debug is disabled. 5 V tolerant.
47 VSS_2 power_in Digital ground. Tie to common system ground.
48 VDD_2 power_in Digital supply, 2.0-3.6 V. Decouple with 100 nF to nearest VSS.
49 PA14 bidirectional After reset: JTCK / SWCLK (SWD clock). Remappable to PA14 GPIO once debug is disabled.
50 PA15 bidirectional After reset: JTDI. Alt: SPI3_NSS/I2S3_WS; remap TIM2_CH1_ETR, PA15 GPIO, SPI1_NSS.
51 PC10 bidirectional GPIO PC10. Alt: UART4_TX; remap USART3_TX, SPI3_SCK, I2S3_CK.
52 PC11 bidirectional GPIO PC11. Alt: UART4_RX; remap USART3_RX, SPI3_MISO.
53 PC12 bidirectional GPIO PC12. Alt: UART5_TX; remap USART3_CK, SPI3_MOSI, I2S3_SD.
54 PD2 bidirectional GPIO PD2. Alt: TIM3_ETR, UART5_RX.
55 PB3 bidirectional After reset: JTDO / TRACESWO. Alt: SPI3_SCK/I2S3_CK; remap PB3 GPIO, TIM2_CH2, SPI1_SCK.
56 PB4 bidirectional After reset: NJTRST (JTAG reset, active low). Alt: SPI3_MISO; remap PB4 GPIO, TIM3_CH1, SPI1_MISO.
57 PB5 bidirectional GPIO PB5 (not 5 V tolerant). Alt: I2C1_SMBA, SPI3_MOSI, ETH_MII_PPS_OUT, I2S3_SD, ETH_RMII_PPS_OUT; remap TIM3_CH2, SPI1_MOSI, CAN2_RX.
58 PB6 bidirectional GPIO PB6. Alt: I2C1_SCL, TIM4_CH1; remap USART1_TX, CAN2_TX.
59 PB7 bidirectional GPIO PB7. Alt: I2C1_SDA, TIM4_CH2; remap USART1_RX.
60 BOOT0 input Boot-mode selection input sampled at reset. Combined with BOOT1 (PB2) selects boot from main Flash, system memory (ST bootloader) or embedded SRAM.
61 PB8 bidirectional GPIO PB8. Alt: TIM4_CH3, ETH_MII_TXD3; remap I2C1_SCL, CAN1_RX.
62 PB9 bidirectional GPIO PB9. Alt: TIM4_CH4; remap I2C1_SDA, CAN1_TX.
63 VSS_3 power_in Digital ground. Tie to common system ground.
64 VDD_3 power_in Digital supply, 2.0-3.6 V. Requires the 4.7 µF bulk capacitor on this pin in addition to a 100 nF decoupling capacitor.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-64(10x10)
Category MCU
Pins 64

Ordering variants

  • STM32F105RCT6
  • STM32F105RCT6STM32F105RCT7
  • STM32F105RCT6STM32F105RBT6
  • STM32F105RCT6STM32F105RBT7
  • STM32F105RCT6STM32F105R8T6
  • STM32F105RCT6STM32F105R8T7
  • STM32F105RCT6STM32F105VCT6
  • STM32F105RCT6STM32F105VCT7
  • STM32F105RCT6STM32F105VBT6
  • STM32F105RCT6STM32F105VBT7
  • STM32F105RCT6STM32F105V8T6
  • STM32F105RCT6STM32F105V8T7
  • STM32F105RCT6STM32F107VCT6
  • STM32F105RCT6STM32F107VCT7
  • STM32F105RCT6STM32F107VBT6
  • STM32F105RCT6STM32F107VBT7
  • STM32F105RCT6STM32F105VCH6
  • STM32F105RCT6STM32F105VCH7
  • STM32F105RCT6STM32F107VCH6
  • STM32F105RCT6STM32F107VCH7

CAD (KiCad official)

  • Symbol: STM32F105RCT6
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (None pp, sha256 04f979ad6ea16a85, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

Schematic Symbol

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PCB Footprint

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