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stm32f091cct6tr
Public Unreviewedby Ray
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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README
markdownSTM32F091CCT6TR
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)
STM32F091CCT6TR from STMicroelectronics, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Backup power supply for RTC and backup registers when VDD is off. Typically 1.8-3.6 V (coin cell). Also powers PC13-PC15 through the internal switch when VDD is absent. |
| 2 | PC13 | bidirectional | Standard 3.3 V (TC) GPIO. Also carries additional functions WKUP2, RTC_TAMP1, RTC_TS, RTC_OUT. Supplied through the RTC power switch (max ~3 mA), so as output limited to 2 MHz / 30 pF and must not source LED currents. |
| 3 | PC14-OSC32_IN | bidirectional | Dual-function pin: after reset it is the OSC32_IN input for the 32.768 kHz LSE crystal; can be reconfigured as PC14 GPIO (TC type). Same power-switch limitations as PC13 apply when used as an output. |
| 4 | PC15-OSC32_OUT | bidirectional | Dual-function pin: OSC32_OUT output of the 32.768 kHz LSE crystal oscillator after reset, or PC15 GPIO (TC type). Same power-switch drive limits as PC13/PC14. |
| 5 | PF0-OSC_IN | bidirectional | Dual-function pin: OSC_IN input for the 4-32 MHz HSE crystal oscillator by default; alternatively PF0 GPIO with alternate functions CRS_SYNC and I2C1_SDA. FTf 5 V-tolerant Fast-Mode-Plus capable. |
| 6 | PF1-OSC_OUT | bidirectional | Dual-function pin: OSC_OUT output for the HSE crystal oscillator by default; alternatively PF1 GPIO with alternate function I2C1_SCL. FTf 5 V-tolerant Fast-Mode-Plus capable. |
| 7 | NRST | bidirectional | Bidirectional device reset pin, active low, with embedded weak pull-up (~40 kΩ). Drives low internally on any reset source; can be pulled low externally to force a full system reset. |
| 8 | VSSA | power_in | Analog ground reference for the ADC, DAC, and comparator blocks. Should be tied to the system ground with careful layout to minimize noise coupling into analog conversions. |
| 9 | VDDA | power_in | Analog supply for the ADC, DAC, comparators, reset block and PLL. Must be between VDD and 3.6 V (2.4-3.6 V required for full ADC accuracy). |
| 10 | PA0 | bidirectional | TTa (3.3 V-tolerant, direct ADC) GPIO. Alternate functions: USART2_CTS, TIM2_CH1_ETR, TSC_G1_IO1, USART4_TX, COMP1_OUT. Additional: RTC_TAMP2, WKUP1, ADC_IN0, COMP1_INM6. |
| 11 | PA1 | bidirectional | TTa GPIO. Alternate: USART2_RTS, TIM2_CH2, TIM15_CH1N, TSC_G1_IO2, USART4_RX, EVENTOUT. Additional: ADC_IN1, COMP1_INP. |
| 12 | PA2 | bidirectional | TTa GPIO. Alternate: USART2_TX, TIM2_CH3, TIM15_CH1, TSC_G1_IO3, COMP2_OUT. Additional: ADC_IN2, WKUP4, COMP2_INM6. |
| 13 | PA3 | bidirectional | TTa GPIO. Alternate: USART2_RX, TIM2_CH4, TIM15_CH2, TSC_G1_IO4. Additional: ADC_IN3, COMP2_INP. |
| 14 | PA4 | bidirectional | TTa GPIO. Alternate: SPI1_NSS, I2S1_WS, TIM14_CH1, TSC_G2_IO1, USART2_CK, USART6_TX. Additional: COMP1_INM4, COMP2_INM4, ADC_IN4, DAC_OUT1. |
| 15 | PA5 | bidirectional | TTa GPIO. Alternate: SPI1_SCK, I2S1_CK, CEC, TIM2_CH1_ETR, TSC_G2_IO2, USART6_RX. Additional: COMP1_INM5, COMP2_INM5, ADC_IN5, DAC_OUT2. |
| 16 | PA6 | bidirectional | TTa GPIO. Alternate: SPI1_MISO, I2S1_MCK, TIM3_CH1, TIM1_BKIN, TIM16_CH1, COMP1_OUT, TSC_G2_IO3, EVENTOUT, USART3_CTS. Additional: ADC_IN6. |
| 17 | PA7 | bidirectional | TTa GPIO. Alternate: SPI1_MOSI, I2S1_SD, TIM3_CH2, TIM14_CH1, TIM1_CH1N, TIM17_CH1, COMP2_OUT, TSC_G2_IO4, EVENTOUT. Additional: ADC_IN7. |
| 18 | PB0 | bidirectional | TTa GPIO. Alternate: TIM3_CH3, TIM1_CH2N, TSC_G3_IO2, EVENTOUT, USART3_CK. Additional: ADC_IN8. |
| 19 | PB1 | bidirectional | TTa GPIO. Alternate: TIM3_CH4, USART3_RTS, TIM14_CH1, TIM1_CH3N, TSC_G3_IO3. Additional: ADC_IN9. |
| 20 | PB2 | bidirectional | 5 V-tolerant (FT) GPIO. Alternate function: TSC_G3_IO4. |
| 21 | PB10 | bidirectional | FTf (5 V-tolerant, Fast-Mode-Plus capable) GPIO. Alternate: SPI2_SCK, I2S2_CK, I2C2_SCL, USART3_TX, CEC, TSC_SYNC, TIM2_CH3. |
| 22 | PB11 | bidirectional | FTf GPIO. Alternate: USART3_RX, TIM2_CH4, EVENTOUT, TSC_G6_IO1, I2C2_SDA. |
| 23 | VSS | power_in | Digital ground reference. Should be connected to the board ground plane; multiple VSS pins provide low-inductance return paths. |
| 24 | VDD | power_in | Digital power supply, 2.0-3.6 V. Provides power to all digital core, GPIO, and peripheral logic; decouple locally with 100 nF near each pin. |
| 25 | PB12 | bidirectional | 5 V-tolerant (FT) GPIO. Alternate: TIM1_BKIN, TIM15_BKIN, SPI2_NSS, I2S2_WS, USART3_CK, TSC_G6_IO2, EVENTOUT. |
| 26 | PB13 | bidirectional | FTf GPIO. Alternate: SPI2_SCK, I2S2_CK, I2C2_SCL, USART3_CTS, TIM1_CH1N, TSC_G6_IO3. |
| 27 | PB14 | bidirectional | FTf GPIO. Alternate: SPI2_MISO, I2S2_MCK, I2C2_SDA, USART3_RTS, TIM1_CH2N, TIM15_CH1, TSC_G6_IO4. |
| 28 | PB15 | bidirectional | FT GPIO. Alternate: SPI2_MOSI, I2S2_SD, TIM1_CH3N, TIM15_CH1N, TIM15_CH2. Additional: WKUP7, RTC_REFIN. |
| 29 | PA8 | bidirectional | FT GPIO powered by VDDIO2. Alternate: USART1_CK, TIM1_CH1, EVENTOUT, MCO, CRS_SYNC. |
| 30 | PA9 | bidirectional | FT GPIO powered by VDDIO2. Alternate: USART1_TX, TIM1_CH2, TIM15_BKIN, MCO, TSC_G4_IO1, I2C1_SCL. |
| 31 | PA10 | bidirectional | FT GPIO powered by VDDIO2. Alternate: USART1_RX, TIM1_CH3, TIM17_BKIN, TSC_G4_IO2, I2C1_SDA. |
| 32 | PA11 | bidirectional | FT GPIO powered by VDDIO2. Alternate: CAN_RX, USART1_CTS, TIM1_CH4, COMP1_OUT, TSC_G4_IO3, EVENTOUT, I2C2_SCL. |
| 33 | PA12 | bidirectional | FT GPIO powered by VDDIO2. Alternate: CAN_TX, USART1_RTS, TIM1_ETR, COMP2_OUT, TSC_G4_IO4, EVENTOUT, I2C2_SDA. |
| 34 | PA13 | bidirectional | Serial-wire debug data pin. FT GPIO powered by VDDIO2, defaults to SWDIO after reset with internal pull-up enabled. Alternate: IR_OUT, SWDIO. |
| 35 | VSS | power_in | Digital ground reference (dedicated return for VDDIO2 domain along with the other VSS pins). |
| 36 | VDDIO2 | power_in | Independent I/O supply (1.65-3.6 V) for PA8-PA15, PC10-PC12, PD0-PD2 and PF6/PC6-PC9 domain - allows mixed-voltage GPIO banks. Must be applied when using any of those pins. |
| 37 | PA14 | bidirectional | Serial-wire debug clock pin. FT GPIO powered by VDDIO2, defaults to SWCLK after reset with internal pull-down enabled. Alternate: USART2_TX, SWCLK. |
| 38 | PA15 | bidirectional | FT GPIO powered by VDDIO2. Alternate: SPI1_NSS, I2S1_WS, USART2_RX, USART4_RTS, TIM2_CH1_ETR, EVENTOUT. |
| 39 | PB3 | bidirectional | FT GPIO. Alternate: SPI1_SCK, I2S1_CK, TIM2_CH2, TSC_G5_IO1, EVENTOUT, USART5_TX. |
| 40 | PB4 | bidirectional | FT GPIO. Alternate: SPI1_MISO, I2S1_MCK, TIM17_BKIN, TIM3_CH1, TSC_G5_IO2, EVENTOUT, USART5_RX. |
| 41 | PB5 | bidirectional | FT GPIO. Alternate: SPI1_MOSI, I2S1_SD, I2C1_SMBA, TIM16_BKIN, TIM3_CH2, USART5_CK_RTS. Additional: WKUP6. |
| 42 | PB6 | bidirectional | FTf GPIO (5 V-tolerant, Fast-Mode-Plus capable). Alternate: I2C1_SCL, USART1_TX, TIM16_CH1N, TSC_G5_IO3. |
| 43 | PB7 | bidirectional | FTf GPIO. Alternate: I2C1_SDA, USART1_RX, USART4_CTS, TIM17_CH1N, TSC_G5_IO4. |
| 44 | PF11-BOOT0 | bidirectional | Boot memory selection at reset - samples high to boot from system memory / SRAM, low to boot from flash. After reset can be reconfigured as PF11 GPIO (FT type). |
| 45 | PB8 | bidirectional | FTf GPIO. Alternate: I2C1_SCL, CEC, TIM16_CH1, TSC_SYNC, CAN_RX. |
| 46 | PB9 | bidirectional | FTf GPIO. Alternate: SPI2_NSS, I2S2_WS, I2C1_SDA, IR_OUT, TIM17_CH1, EVENTOUT, CAN_TX. |
| 47 | VSS | power_in | Digital ground reference. |
| 48 | VDD | power_in | Digital power supply, 2.0-3.6 V. Decouple locally with 100 nF near the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-48(7x7) |
| Category | MCU |
| Pins | 48 |
Ordering variants
STM32F091CCT6TRSTM32F091CBT6STM32F091CCT6TRSTM32F091CBT6TRSTM32F091CCT6TRSTM32F091CBT7STM32F091CCT6TRSTM32F091CBT7TRSTM32F091CCT6TRSTM32F091CCT6TRSTM32F091CCT7STM32F091CCT6TRSTM32F091CCT7TRSTM32F091CCT6TRSTM32F091CBU6STM32F091CCT6TRSTM32F091CBU6TRSTM32F091CCT6TRSTM32F091CBU7STM32F091CCT6TRSTM32F091CBU7TRSTM32F091CCT6TRSTM32F091CCU6STM32F091CCT6TRSTM32F091CCU6TRSTM32F091CCT6TRSTM32F091CCU7STM32F091CCT6TRSTM32F091CCU7TRSTM32F091CCT6TRSTM32F091RBT6STM32F091CCT6TRSTM32F091RBT6TRSTM32F091CCT6TRSTM32F091RBT7STM32F091CCT6TRSTM32F091RBT7TRSTM32F091CCT6TRSTM32F091RCT6STM32F091CCT6TRSTM32F091RCT6TRSTM32F091CCT6TRSTM32F091RCT7STM32F091CCT6TRSTM32F091RCT7TRSTM32F091CCT6TRSTM32F091RBH6STM32F091CCT6TRSTM32F091RBH6TRSTM32F091CCT6TRSTM32F091RCH6STM32F091CCT6TRSTM32F091RCH6TRSTM32F091CCT6TRSTM32F091RBY6STM32F091CCT6TRSTM32F091RBY6TRSTM32F091CCT6TRSTM32F091RCY6STM32F091CCT6TRSTM32F091RCY6TRSTM32F091CCT6TRSTM32F091VBT6STM32F091CCT6TRSTM32F091VBT6TRSTM32F091CCT6TRSTM32F091VCT6STM32F091CCT6TRSTM32F091VCT6TRSTM32F091CCT6TRSTM32F091VBT7STM32F091CCT6TRSTM32F091VCT7STM32F091CCT6TRSTM32F091VBH6STM32F091CCT6TRSTM32F091VBH6TRSTM32F091CCT6TRSTM32F091VCH6STM32F091CCT6TRSTM32F091VCH6TR
CAD (KiCad official)
- Symbol:
STM32F091CCT6TR - Footprint:
Package_QFP:LQFP-48_7x7mm_P0.5mm - 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (None pp, sha256
f96a82f50344c619, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).