component
stiso621tr
Public Unreviewedby Ray
STMicroelectronics Digital Isolators, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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README
markdownSTISO621TR
STMicroelectronics · Digital Isolators · SOIC-8
STISO621TR from STMicroelectronics, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Supply voltage for side 1 (3 V to 5.5 V recommended; -0.3 V to 7 V absolute max). Powers the side-1 transmitter/receiver stages. Decouple to GND1 with a local bypass capacitor. |
| 2 | RX1 | output | Receive data output on side 1. CMOS logic output driven by the isolated data received from TX2 on side 2 (VOH >= VDD1-0.3 V at IOH=4 mA; VOL <= 0.4 V at IOL=4 mA). Defaults to safe state L after watchdog timeout when the opposite side is below UVLO. |
| 3 | TX1 | input | Transmit data input on side 1. Schmitt-trigger CMOS logic input (VILH<=2 V, VIHL>=0.8 V, ~0.5 V hysteresis); data is transmitted across the isolation barrier and appears at RX2 on side 2. |
| 4 | GND1 | power_in | Ground reference for side 1. Isolated from GND2 by the internal thick-oxide isolation barrier (up to 6 kV isolation withstand voltage). |
| 5 | GND2 | power_in | Ground reference for side 2. Isolated from GND1 by the internal thick-oxide isolation barrier. |
| 6 | RX2 | output | Receive data output on side 2. CMOS logic output driven by the isolated data received from TX1 on side 1 (VOH >= VDD2-0.3 V at IOH=4 mA; VOL <= 0.4 V at IOL=4 mA). Defaults to safe state L after watchdog timeout when side 1 is below UVLO. |
| 7 | TX2 | input | Transmit data input on side 2. Schmitt-trigger CMOS logic input (VILH<=2 V, VIHL>=0.8 V, ~0.5 V hysteresis); data is transmitted across the isolation barrier and appears at RX1 on side 1. |
| 8 | VDD2 | power_in | Supply voltage for side 2 (3 V to 5.5 V recommended; -0.3 V to 7 V absolute max). Powers the side-2 transmitter/receiver stages. Decouple to GND2 with a local bypass capacitor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SOIC-8 |
| Category | Comm/UART |
| Pins | 8 |
Ordering variants
Same part, different packaging or reel option.
STISO621TRSTISO621WSTISO621WTR
CAD (KiCad official)
- Symbol:
STISO621TR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (21 pp, sha256
eb02694ca421752d, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).
Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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