STC8H3K64S2-45I-TSSOP20
Public Unreviewedby Ray
STC Micro Microcontrollers (MCU/MPU/SOC), TSSOP-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Symbol & Footprint
Schematic Symbol
Open full view ↗PCB Footprint
Open full view ↗Datasheet
Open in new tab ↗Contents
README
markdownSTC8H3K64S2-45I-TSSOP20
STC Micro · Microcontrollers (MCU/MPU/SOC) · TSSOP-20
STC8H3K64S2-45I-TSSOP20 from STC Micro, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P1.0/ADC0/RxD2/PWM1P | bidirectional | Standard I/O P1.0; muxed with ADC channel 0 input, UART2 receive (RxD2), and PWM1 positive capture/output (PWM1P). Power-on state is high-impedance input (must be configured before use). |
| 2 | P1.6/ADC6/RxD_3/PWM4P/MCLKO_2/XTALO | bidirectional | Standard I/O P1.6; muxed with ADC channel 6, UART1 receive alt-3 (RxD_3), PWM4 positive output, master clock divided output (MCLKO_2), and external crystal output (XTALO). |
| 3 | P1.7/ADC7/TxD_3/PWM4N/PWM5_2/XTALI | bidirectional | Standard I/O P1.7; muxed with ADC channel 7, UART1 transmit alt-3 (TxD_3), PWM4 negative output, PWM5 capture/output alt-2, and external crystal/clock input (XTALI). |
| 4 | AGnd | power_in | ADC analog ground reference. Should be tied to the system ground plane at a single point near the MCU for best analog performance. |
| 5 | ADC_VRef+ | power_in | ADC external positive reference input, 2.4 V to MCU-VCC. Must be tied to an external reference (or AVcc for low-precision applications); leaving floating produces leakage current. |
| 6 | AVcc | power_in | ADC analog supply pin (1.9 V to 5.5 V, matched to VCC). Decouple with 0.1 uF close to the pin. |
| 7 | P5.4/nRST/MCLKO/SS_3/PWM6_2 | bidirectional | Standard I/O P5.4; muxed with active-low external reset (nRST), master clock output (MCLKO), SPI slave-select alt-3 (SS_3), and PWM6 capture/output alt-2. Default at factory is P5.4 I/O; nRST function must be enabled via ISP option, which takes effect after a power cycle. |
| 8 | Vcc | power_in | Main digital supply pin, 1.9 V to 5.5 V. Bulk decoupling of 10 uF plus 0.1 uF between Vcc and Gnd is recommended, placed close to the chip. |
| 9 | P5.5 | bidirectional | Standard general-purpose I/O port pin P5.5. Power-on state is high-impedance input; configure the port mode register before use. |
| 10 | Gnd | power_in | Digital ground return for the main Vcc rail. |
| 11 | P3.0/RxD/INT4 | bidirectional | Standard I/O P3.0; muxed with UART1 receive (RxD) and external interrupt 4 (INT4). Also used together with P3.1/P3.2 by the mask-ROM bootloader to detect USB-ISP entry at reset. |
| 12 | P3.1/TxD | bidirectional | Standard I/O P3.1; muxed with UART1 transmit (TxD). Powers up in weak pull-up (quasi-bidirectional) mode. |
| 13 | P3.2/INT0/SCLK_4/SCL_4/PWMETI/PWMETI2 | bidirectional | Standard I/O P3.2; muxed with external interrupt 0 (INT0), SPI clock alt-4 (SCLK_4), I2C clock alt-4 (SCL_4), and PWM external trigger inputs (PWMETI, PWMETI2). |
| 14 | P3.3/INT1/MISO_4/SDA_4/PWM4N_4/PWM7_2 | bidirectional | Standard I/O P3.3; muxed with external interrupt 1 (INT1), SPI MISO alt-4, I2C SDA alt-4, PWM4 negative output alt-4, and PWM7 capture/output alt-2. |
| 15 | P3.4/T0/T1CLKO/MOSI_4/PWM4P_4/PWM8_2/CMPO | bidirectional | Standard I/O P3.4; muxed with Timer 0 external clock input (T0), Timer 1 divided clock output (T1CLKO), SPI MOSI alt-4, PWM4 positive output alt-4, PWM8 capture/output alt-2, and analog comparator output (CMPO). |
| 16 | P3.5/T1/T0CLKO/SS_4/PWMFLT | bidirectional | Standard I/O P3.5; muxed with Timer 1 external clock input (T1), Timer 0 divided clock output (T0CLKO), SPI slave-select alt-4 (SS_4), and enhanced-PWM external fault input (PWMFLT). |
| 17 | P3.6/INT2/RxD_2/CMP- | bidirectional | Standard I/O P3.6; muxed with external interrupt 2 (INT2), UART1 receive alt-2 (RxD_2), and the analog comparator negative input (CMP-). |
| 18 | P3.7/INT3/TxD_2/CMP+ | bidirectional | Standard I/O P3.7; muxed with external interrupt 3 (INT3), UART1 transmit alt-2 (TxD_2), and the analog comparator positive input (CMP+). |
| 19 | P1.2/ADC2/PWM2P/SS/T2 | bidirectional | Standard I/O P1.2; muxed with ADC channel 2, PWM2 positive capture/output (PWM2P), SPI slave-select (SS), and Timer 2 external clock input (T2). |
| 20 | P1.1/ADC1/TxD2/PWM1N | bidirectional | Standard I/O P1.1; muxed with ADC channel 1, UART2 transmit (TxD2), and PWM1 negative output (PWM1N). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STC Micro |
| Package | TSSOP-20 |
| Category | MCU |
| Pins | 20 |
Ordering variants
Same part, different packaging or reel option.
STC8H3K64S2-45I-TSSOP20STC8H3K64S2-45I-LQFP48STC8H3K64S2-45I-QFN48STC8H3K64S2-45I-LQFP32STC8H3K64S2-45I-QFN32STC8H3K64S2-45I-PDIP40
CAD (KiCad official)
- Symbol:
STC8H3K64S2-45I-TSSOP20 - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
stc8h3k64s2-45i-tssop20.step |
267 KB | You want the bare part, or you mark your own boards. |
stc8h3k64s2-45i-tssop20-etched.step |
5.0 MB | You want the part with STC8H3K64S2-45I-TSSOP20 already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 1215 faces against 327 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STC Micro datasheet (2180 pp, sha256
046aea020e4685f3, retrieved 2026-08-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).