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STC8G1K17-38I-TSSOP20
Public Unreviewedby Ray
STC Micro Microcontrollers (MCU/MPU/SOC), TSSOP-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.
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markdownSTC8G1K17-38I-TSSOP20
STC Micro · Microcontrollers (MCU/MPU/SOC) · TSSOP-20
STC8G1K17-38I-TSSOP20 from STC Micro, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P1.2/ADC2/SS/T2/ECI | bidirectional | Standard I/O port P1.2. Muxed with ADC channel 2 input, SPI slave-select (SS), Timer 2 external clock input (T2), and PCA external pulse input (ECI). |
| 2 | P1.3/ADC3/MOSI/T2CLKO | bidirectional | Standard I/O port P1.3. Muxed with ADC channel 3 input, SPI master-out/slave-in (MOSI), and Timer 2 clock divided output (T2CLKO). |
| 3 | P1.4/ADC4/MISO/SDA | bidirectional | Standard I/O port P1.4. Muxed with ADC channel 4 input, SPI master-in/slave-out (MISO), and I2C data line (SDA). |
| 4 | P1.5/ADC5/SCLK/SCL | bidirectional | Standard I/O port P1.5. Muxed with ADC channel 5 input, SPI clock (SCLK), and I2C clock line (SCL). |
| 5 | P1.6/ADC6/RxD_3/MCLKO_2/XTALO | bidirectional | Standard I/O port P1.6. Muxed with ADC channel 6, UART1 receive (alt 3), master clock divided output (alt 2), and external crystal output (XTALO). |
| 6 | P1.7/ADC7/TxD_3/XTALI | bidirectional | Standard I/O port P1.7. Muxed with ADC channel 7, UART1 transmit (alt 3), and external crystal input (XTALI). |
| 7 | P5.4/nRST/MCLKO | bidirectional | Standard I/O port P5.4. Configurable via ISP option as active-low reset input (nRST) or master clock divided output (MCLKO). When configured as reset the internal 4k pull-up is always enabled; as GPIO the pull-up stays enabled for ~6.5ms at power-up before auto-disabling. |
| 8 | VCC/AVCC/ADC_VRef+ | power_in | Positive supply pin for the MCU digital core, analog VCC, and the ADC positive reference input (ADC_VRef+). Supply range 1.9-5.5V. If a separate ADC reference is not driven, tie ADC_VRef+ to MCU VCC (floating causes leakage). |
| 9 | P5.5 | bidirectional | Standard I/O port P5.5 with no alternate functions on this package. |
| 10 | GND/AGND | power_in | Ground reference for digital core (Gnd) and analog/ADC (AGnd). Combined on a single package pin. |
| 11 | P3.0/RxD/ADC8/INT4 | bidirectional | Standard I/O port P3.0. Muxed with UART1 receive (RxD), ADC channel 8, and external interrupt 4 (INT4). Powers up in weak pull-up quasi-bidirectional mode. |
| 12 | P3.1/TxD/ADC9 | bidirectional | Standard I/O port P3.1. Muxed with UART1 transmit (TxD) and ADC channel 9. Powers up in weak pull-up quasi-bidirectional mode. |
| 13 | P3.2/INT0/ADC10/SCL_4/SCLK_4 | bidirectional | Standard I/O port P3.2. Muxed with external interrupt 0 (INT0), ADC channel 10, I2C clock (SCL alt 4), and SPI clock (SCLK alt 4). |
| 14 | P3.3/INT1/ADC11/SDA_4/MISO_4 | bidirectional | Standard I/O port P3.3. Muxed with external interrupt 1 (INT1), ADC channel 11, I2C data (SDA alt 4), and SPI MISO (alt 4). |
| 15 | P3.4/T0/T1CLKO/ADC12/ECI_2/CMPO/MOSI_4 | bidirectional | Standard I/O port P3.4. Muxed with Timer 0 external clock (T0), Timer 1 divided clock output (T1CLKO), ADC channel 12, PCA external pulse input (ECI alt 2), comparator output (CMPO), and SPI MOSI (alt 4). |
| 16 | P3.5/T1/T0CLKO/ADC13/CCP0_2/SS_4 | bidirectional | Standard I/O port P3.5. Muxed with Timer 1 external clock (T1), Timer 0 divided clock output (T0CLKO), ADC channel 13, PCA CCP0 capture/PWM (alt 2), and SPI slave-select (SS alt 4). |
| 17 | P3.6/INT2/RxD_2/ADC14/CCP1_2/CMP- | bidirectional | Standard I/O port P3.6. Muxed with external interrupt 2 (INT2), UART1 receive (alt 2), ADC channel 14, PCA CCP1 capture/PWM (alt 2), and comparator negative input (CMP-). |
| 18 | P3.7/INT3/TxD_2/CCP2/CCP2_2/CMP+ | bidirectional | Standard I/O port P3.7. Muxed with external interrupt 3 (INT3), UART1 transmit (alt 2), PCA CCP2 capture/PWM (default and alt 2 groups), and comparator positive input (CMP+). |
| 19 | P1.0/RxD2/ADC0/CCP1 | bidirectional | Standard I/O port P1.0. Muxed with UART2 receive (RxD2), ADC channel 0, and PCA CCP1 capture/PWM. |
| 20 | P1.1/TxD2/ADC1/CCP0 | bidirectional | Standard I/O port P1.1. Muxed with UART2 transmit (TxD2), ADC channel 1, and PCA CCP0 capture/PWM. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STC Micro |
| Package | TSSOP-20 |
| Category | MCU |
| Pins | 20 |
Ordering variants
Same part, different packaging or reel option.
STC8G1K17-38I-TSSOP20STC8G1K17-38I-QFN20STC8G1K17-38I-SOP16
CAD (KiCad official)
- Symbol:
STC8G1K17-38I-TSSOP20 - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STC Micro datasheet (1240 pp, sha256
7d5e82c9f651aa92, retrieved 2026-08-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).