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stc89c58rd-40i-lqfp44

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STC Micro STC89C58RD 40I LQFP44 Microcontrollers (MCU/MPU/SOC), LQFP-44(10x10). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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STC89C58RD+40I-LQFP44

STC Micro STC89C58RD 40I LQFP44 · Microcontrollers (MCU/MPU/SOC) · LQFP-44(10x10)

STC89C58RD+40I-LQFP44 from STC Micro STC89C58RD 40I LQFP44, in a LQFP-44(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P1.5 bidirectional Standard I/O port PORT1[5]. Quasi-bidirectional with internal weak pull-up.
2 P1.6 bidirectional Standard I/O port PORT1[6]. Quasi-bidirectional with internal weak pull-up.
3 P1.7 bidirectional Standard I/O port PORT1[7]. Quasi-bidirectional with internal weak pull-up.
4 RST input External reset input. Active high; hold high for >= 24 clocks to reset the MCU. Internal POR/BOD provided, external RC network typically not required.
5 P3.0/RxD bidirectional P3.0 general purpose I/O; alternate function RxD, UART1 serial data receive input.
6 P4.3/INT2 bidirectional P4.3 general purpose I/O; alternate function INT2, external interrupt 2 (falling-edge or low-level trigger).
7 P3.1/TxD bidirectional P3.1 general purpose I/O; alternate function TxD, UART1 serial data transmit output.
8 P3.2/INT0 bidirectional P3.2 general purpose I/O; alternate function INT0, external interrupt 0 (falling-edge or low-level trigger).
9 P3.3/INT1 bidirectional P3.3 general purpose I/O; alternate function INT1, external interrupt 1 (falling-edge or low-level trigger).
10 P3.4/T0 bidirectional P3.4 general purpose I/O; alternate function T0, external count input for Timer/Counter 0.
11 P3.5/T1 bidirectional P3.5 general purpose I/O; alternate function T1, external count input for Timer/Counter 1.
12 P3.6/WR bidirectional P3.6 general purpose I/O; alternate function WR, active-low external data-memory write strobe (used with MOVX to external XRAM).
13 P3.7/RD bidirectional P3.7 general purpose I/O; alternate function RD, active-low external data-memory read strobe (used with MOVX to external XRAM).
14 XTAL2 output Inverting oscillator amplifier output. Connect to one lead of the external crystal (with a load cap to GND). May be left floating when an external clock source drives XTAL1.
15 XTAL1 input Inverting oscillator amplifier input; also the external clock input. Connect to the other lead of the crystal (with a load cap to GND) or drive with a CMOS clock (typ. 47 pF load caps for crystal, 0-40 MHz).
16 GND power_in Ground / 0 V return for the digital core and I/O.
17 P4.0 bidirectional Standard I/O port PORT4[0]. Quasi-bidirectional with internal weak pull-up.
18 P2.0/A8 bidirectional P2.0 general purpose I/O with internal pull-up; alternate function A8, external-memory address bus bit 8 (asserted during MOVX / external code fetch).
19 P2.1/A9 bidirectional P2.1 general purpose I/O with internal pull-up; alternate function A9, external-memory address bit 9.
20 P2.2/A10 bidirectional P2.2 general purpose I/O with internal pull-up; alternate function A10, external-memory address bit 10.
21 P2.3/A11 bidirectional P2.3 general purpose I/O with internal pull-up; alternate function A11, external-memory address bit 11.
22 P2.4/A12 bidirectional P2.4 general purpose I/O with internal pull-up; alternate function A12, external-memory address bit 12.
23 P2.5/A13 bidirectional P2.5 general purpose I/O with internal pull-up; alternate function A13, external-memory address bit 13.
24 P2.6/A14 bidirectional P2.6 general purpose I/O with internal pull-up; alternate function A14, external-memory address bit 14.
25 P2.7/A15 bidirectional P2.7 general purpose I/O with internal pull-up; alternate function A15, external-memory address bit 15.
26 P4.4/PSEN bidirectional HD-version P4.4 general purpose I/O; alternate function PSEN, active-low program-store-enable strobe for external program memory fetch. On '90C' silicon this pad is P4.4 only (PSEN unavailable).
27 P4.5/ALE bidirectional P4.5 general purpose I/O; alternate function ALE, address-latch-enable output for external memory demux and Vpp/programming pulse input. Default function is ALE; to use as P4.5 the ALEOFF bit (or 90C ISP option) must be set.
28 P4.1 bidirectional Standard I/O port PORT4[1]. Quasi-bidirectional with internal weak pull-up.
29 P4.6/EA bidirectional HD-version P4.6 general purpose I/O; alternate function EA (External Access) - tie high for internal Flash execution, tie low to force external program memory. On '90C' silicon this pad is P4.6 only (no EA function).
30 P0.7/AD7 bidirectional P0.7 open-drain I/O (external pull-up 4.7-10 k required for GPIO use); alternate function AD7, multiplexed A7/D7 line for external memory bus.
31 P0.6/AD6 bidirectional P0.6 open-drain I/O (needs external pull-up); alternate function AD6, multiplexed A6/D6 line for external memory bus.
32 P0.5/AD5 bidirectional P0.5 open-drain I/O (needs external pull-up); alternate function AD5, multiplexed A5/D5 line for external memory bus.
33 P0.4/AD4 bidirectional P0.4 open-drain I/O (needs external pull-up); alternate function AD4, multiplexed A4/D4 line for external memory bus.
34 P0.3/AD3 bidirectional P0.3 open-drain I/O (needs external pull-up); alternate function AD3, multiplexed A3/D3 line for external memory bus.
35 P0.2/AD2 bidirectional P0.2 open-drain I/O (needs external pull-up); alternate function AD2, multiplexed A2/D2 line for external memory bus.
36 P0.1/AD1 bidirectional P0.1 open-drain I/O (needs external pull-up); alternate function AD1, multiplexed A1/D1 line for external memory bus.
37 P0.0/AD0 bidirectional P0.0 open-drain I/O (needs external pull-up); alternate function AD0, multiplexed A0/D0 line for external memory bus.
38 VCC power_in Positive supply. 3.3-5.5 V for STC89Cxx (C-suffix); 2.0-3.6 V for STC89LExx (LE low-voltage variants). Recommend local 10 uF + 0.1 uF decoupling to GND.
39 P4.2/INT3 bidirectional P4.2 general purpose I/O; alternate function INT3, external interrupt 3 (falling-edge or low-level trigger).
40 P1.0/T2 bidirectional P1.0 general purpose I/O; alternate function T2, external count / clock input for Timer/Counter 2.
41 P1.1/T2EX bidirectional P1.1 general purpose I/O; alternate function T2EX, Timer 2 capture/reload trigger input.
42 P1.2 bidirectional Standard I/O port PORT1[2]. Quasi-bidirectional with internal weak pull-up.
43 P1.3 bidirectional Standard I/O port PORT1[3]. Quasi-bidirectional with internal weak pull-up.
44 P1.4 bidirectional Standard I/O port PORT1[4]. Quasi-bidirectional with internal weak pull-up.

Key specifications

Parameter Value
Manufacturer STC Micro STC89C58RD 40I LQFP44
Package LQFP-44(10x10)
Category MCU
Pins 44

Ordering variants

  • STC89C58RD+40I-LQFP44
  • STC89C58RD+40I-LQFP4435I-LQFP44
  • STC89C58RD+40I-LQFP4440I-PDIP40
  • STC89C58RD+40I-LQFP4435I-PDIP40
  • STC89C58RD+40I-LQFP4440I-PLCC44

CAD (KiCad official)

  • Symbol: STC89C58RD+40I-LQFP44
  • Footprint: Package_QFP:LQFP-44_10x10mm_P0.8mm
  • 3D model: LQFP-44(10x10) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STC Micro STC89C58RD 40I LQFP44 datasheet (None pp, sha256 fac7be430b93e2dd, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

Schematic Symbol

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PCB Footprint

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