STC89C52RC-40I-PDIP40 from STC Micro, in a DIP-40. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	P1.0/T2	bidirectional	Port 1 bit 0 quasi-bidirectional I/O with internal pull-up. Alt: T2 external input for Timer/Counter 2.
2	P1.1/T2EX	bidirectional	Port 1 bit 1 quasi-bidirectional I/O with internal pull-up. Alt: T2EX trigger for Timer/Counter 2 capture/reload.
3	P1.2	bidirectional	Port 1 bit 2 quasi-bidirectional I/O with internal pull-up.
4	P1.3	bidirectional	Port 1 bit 3 quasi-bidirectional I/O with internal pull-up.
5	P1.4	bidirectional	Port 1 bit 4 quasi-bidirectional I/O with internal pull-up.
6	P1.5	bidirectional	Port 1 bit 5 quasi-bidirectional I/O with internal pull-up.
7	P1.6	bidirectional	Port 1 bit 6 quasi-bidirectional I/O with internal pull-up. Optional external crystal connection point on some board designs.
8	P1.7	bidirectional	Port 1 bit 7 quasi-bidirectional I/O with internal pull-up. Optional external crystal connection point on some board designs.
9	RST	input	Reset input. Active-high reset. RC/RD+ HD-version parts include an internal 45 kΩ-100 kΩ pull-down on this pin; an external RC network (10 uF + 10 kΩ) may also be used.
10	P3.0/RxD	bidirectional	Port 3 bit 0 quasi-bidirectional I/O with internal pull-up. Alt: UART1 serial data receive input (RxD).
11	P3.1/TxD	bidirectional	Port 3 bit 1 quasi-bidirectional I/O with internal pull-up. Alt: UART1 serial data transmit output (TxD).
12	P3.2/INT0	bidirectional	Port 3 bit 2 quasi-bidirectional I/O with internal pull-up. Alt: INT0 external interrupt 0 (falling-edge or low-level triggered).
13	P3.3/INT1	bidirectional	Port 3 bit 3 quasi-bidirectional I/O with internal pull-up. Alt: INT1 external interrupt 1 (falling-edge or low-level triggered).
14	P3.4/T0	bidirectional	Port 3 bit 4 quasi-bidirectional I/O with internal pull-up. Alt: T0 external clock input for Timer/Counter 0.
15	P3.5/T1	bidirectional	Port 3 bit 5 quasi-bidirectional I/O with internal pull-up. Alt: T1 external clock input for Timer/Counter 1.
16	P3.6/WR	bidirectional	Port 3 bit 6 quasi-bidirectional I/O with internal pull-up. Alt: /WR external data memory write strobe (active-low) for MOVX access to external XRAM.
17	P3.7/RD	bidirectional	Port 3 bit 7 quasi-bidirectional I/O with internal pull-up. Alt: /RD external data memory read strobe (active-low) for MOVX access to external XRAM.
18	XTAL2	output	On-chip clock oscillator inverting amplifier output. Connect to one lead of the external crystal. If an external clock source drives XTAL1 directly, XTAL2 may be left floating or used as a buffered clock output.
19	XTAL1	input	On-chip clock oscillator inverting amplifier input. Connect to one lead of the external crystal (typ. 4 MHz-48 MHz). Also serves as the external clock source input.
20	GND	power_in	Ground / 0 V power supply return.
21	P2.0/A8	bidirectional	Port 2 bit 0 quasi-bidirectional I/O with internal pull-up. Alt: A8 high-order address bus bit when accessing external memory.
22	P2.1/A9	bidirectional	Port 2 bit 1 quasi-bidirectional I/O with internal pull-up. Alt: A9 high-order address bus bit when accessing external memory.
23	P2.2/A10	bidirectional	Port 2 bit 2 quasi-bidirectional I/O with internal pull-up. Alt: A10 high-order address bus bit when accessing external memory.
24	P2.3/A11	bidirectional	Port 2 bit 3 quasi-bidirectional I/O with internal pull-up. Alt: A11 high-order address bus bit when accessing external memory.
25	P2.4/A12	bidirectional	Port 2 bit 4 quasi-bidirectional I/O with internal pull-up. Alt: A12 high-order address bus bit when accessing external memory.
26	P2.5/A13	bidirectional	Port 2 bit 5 quasi-bidirectional I/O with internal pull-up. Alt: A13 high-order address bus bit when accessing external memory.
27	P2.6/A14	bidirectional	Port 2 bit 6 quasi-bidirectional I/O with internal pull-up. Alt: A14 high-order address bus bit when accessing external memory.
28	P2.7/A15	bidirectional	Port 2 bit 7 quasi-bidirectional I/O with internal pull-up. Alt: A15 high-order address bus bit when accessing external memory.
29	P4.4/PSEN	bidirectional	HD-version: /PSEN external program-memory strobe output (active-low). 90C-version: P4.4 general-purpose quasi-bidirectional I/O.
30	P4.5/ALE	bidirectional	Address-latch-enable output that strobes the low byte of address during external memory access; also serves as the programming pulse input during ISP. On the 90C version this pin can be reconfigured as GPIO P4.5.
31	P4.6/EA	bidirectional	HD-version: /EA external access enable input; tie low to force execution from external program memory, high (or leave with internal pull-up) to execute from internal Flash. 90C-version: P4.6 general-purpose quasi-bidirectional I/O.
32	P0.7/AD7	bidirectional	Port 0 bit 7 8-bit quasi-bidirectional I/O; open-drain after power-on reset, so an external 4.7 kΩ-10 kΩ pull-up is required when used as GPIO. Alt: AD7 multiplexed low-byte address/data bit 7 during external memory access (no external pull-up needed in this mode).
33	P0.6/AD6	bidirectional	Port 0 bit 6 8-bit quasi-bidirectional I/O; open-drain after power-on reset (external 4.7 kΩ-10 kΩ pull-up required for I/O use). Alt: AD6 multiplexed low-byte address/data bit 6.
34	P0.5/AD5	bidirectional	Port 0 bit 5 8-bit quasi-bidirectional I/O; open-drain after power-on reset (external 4.7 kΩ-10 kΩ pull-up required for I/O use). Alt: AD5 multiplexed low-byte address/data bit 5.
35	P0.4/AD4	bidirectional	Port 0 bit 4 8-bit quasi-bidirectional I/O; open-drain after power-on reset (external 4.7 kΩ-10 kΩ pull-up required for I/O use). Alt: AD4 multiplexed low-byte address/data bit 4.
36	P0.3/AD3	bidirectional	Port 0 bit 3 8-bit quasi-bidirectional I/O; open-drain after power-on reset (external 4.7 kΩ-10 kΩ pull-up required for I/O use). Alt: AD3 multiplexed low-byte address/data bit 3.
37	P0.2/AD2	bidirectional	Port 0 bit 2 8-bit quasi-bidirectional I/O; open-drain after power-on reset (external 4.7 kΩ-10 kΩ pull-up required for I/O use). Alt: AD2 multiplexed low-byte address/data bit 2.
38	P0.1/AD1	bidirectional	Port 0 bit 1 8-bit quasi-bidirectional I/O; open-drain after power-on reset (external 4.7 kΩ-10 kΩ pull-up required for I/O use). Alt: AD1 multiplexed low-byte address/data bit 1.
39	P0.0/AD0	bidirectional	Port 0 bit 0 8-bit quasi-bidirectional I/O; open-drain after power-on reset (external 4.7 kΩ-10 kΩ pull-up required for I/O use). Alt: AD0 multiplexed low-byte address/data bit 0.
40	VCC	power_in	Positive supply voltage. 5.0 V parts operate 2 MHz-48 MHz; 3.3 V parts operate 2 MHz-48 MHz (12T) / 2 MHz-32 MHz (6T). Decouple with ≥10 uF bulk plus 0.1 uF ceramic near the pin.

Key specifications

Parameter	Value
Manufacturer	STC Micro
Package	DIP-40
Category	MCU
Pins	40

Ordering variants

Same part, different packaging or reel option.

STC89C52RC-40I-PDIP40
STC89C52RC-40I-PDIP40LQFP44
STC89C52RC-40I-PDIP40PLCC44

CAD (KiCad official)

Symbol: STC89C52RC-40I-PDIP40
Footprint: Package_DIP:DIP-40_W25.4mm
3D model: DIP-40 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STC Micro datasheet (1691 pp, sha256 fac7be430b93e2dd, retrieved 2026-08-17, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF