component
STBB1-APUR
Public Unreviewedby Ray
STMicroelectronics DC-DC Converters, DFN-10-EP(3x3). Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownSTBB1-APUR
STMicroelectronics · DC-DC Converters · DFN-10-EP(3x3)
STBB1-APUR from STMicroelectronics, in a DFN-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUT | power_out | Output voltage of the buck-boost converter. Adjustable from 1.2 V to 5.5 V set by the R1/R2 feedback divider. Connect the output bypass capacitor (COUT, e.g. 22 µF) between this pin and PGND. |
| 2 | SW2 | passive | Switch node 2. Internal power MOSFETs (N-ch and P-ch) are connected to this pin. Connect the external 2.2 µH inductor between SW1 (pin 4) and SW2. Peak switch current up to 2.3 A. |
| 3 | PGND | power_in | Power ground. Return path for the power-stage MOSFETs; tie to the ground plane together with the exposed pad and the input/output bypass capacitor grounds. |
| 4 | SW1 | passive | Switch node 1. Internal power MOSFETs are connected to this pin. Connect the external 2.2 µH inductor between SW1 and SW2 (pin 2). |
| 5 | VIN | power_in | Power input voltage, 2.0 V to 5.5 V (absolute max -0.3 V to 7 V). Connect a ceramic bypass capacitor (10 µF minimum) between this pin and PGND. |
| 6 | EN | input | Enable pin. Drive below 0.4 V (or tie to GND) to shut down the IC; drive above 1.2 V to enable. Shutdown current < 1 µA. |
| 7 | MODE/SYNC | input | Operation mode selection / external sync input. Low = auto mode (pulse skipping at light load, PWM at higher load); high = forced fixed-frequency PWM. Applying a square-wave clock synchronizes the internal 1.5 MHz oscillator. |
| 8 | VINA | power_in | Supply voltage for the analog/control stage. Typically tied to VIN (2.0 V to 5.5 V); decouple locally to signal ground. |
| 9 | GND | power_in | Signal ground for the analog control section. Tie to the ground plane; keep noisy power-stage return currents on PGND. |
| 10 | FB | input | Feedback voltage input to the error amplifier. Connect to the R1/R2 divider from VOUT; internal reference sets the regulation target (R1 = R2 × (VOUT/VFB − 1); suggested R2 = 100 kΩ). |
| EP | EP | power_in | Exposed thermal pad on the underside of the DFN-10 package. Electrically connected to power ground; solder to a copper ground pad for thermal dissipation (RthJC = 2.96 °C/W, RthJA = 30.9 °C/W). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | DFN-10-EP(3x3) |
| Category | PMIC |
| Pins | 11 |
Ordering variants
Same part, different packaging or reel option.
STBB1-APUR
CAD (KiCad official)
- Symbol:
STBB1-APUR - Footprint:
Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm - 3D model: DFN-10-EP(3x3) (KiCad packages3D, STEP)
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
stbb1-apur.step |
126 KB | You want the bare part, or you mark your own boards. |
stbb1-apur-etched.step |
1.8 MB | You want the part with STBB1-APUR already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 457 faces against 74 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (23 pp, sha256
9e286b1afe39df29, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).