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SSD2831QL9

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Solomon Systech Video Interface ICs, LQFP-128(14x14). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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SSD2831QL9

Solomon Systech · Video Interface ICs · LQFP-128(14x14)

SSD2831QL9 from Solomon Systech, in a LQFP-128(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AVDD power_in Analog power supply, 1.2 V.
2 RX0_DP2 output MIPI DSI RX0 data lane 2 positive.
3 RX0_DN2 output MIPI DSI RX0 data lane 2 negative.
4 AVSS power_in Analog ground return.
5 RX0_DP1 output MIPI DSI RX0 data lane 1 positive.
6 RX0_DN1 output MIPI DSI RX0 data lane 1 negative.
7 VSS power_in Digital ground return.
8 RX0_CP output MIPI DSI RX0 clock lane positive.
9 RX0_CN output MIPI DSI RX0 clock lane negative.
10 AVDD power_in Analog power supply, 1.2 V.
11 AVSS power_in Analog ground return.
12 RX0_DP0 bidirectional MIPI DSI RX0 data lane 0 positive (LP bidirectional).
13 RX0_DN0 bidirectional MIPI DSI RX0 data lane 0 negative (LP bidirectional).
14 AVSS power_in Analog ground return.
15 RX0_DP3 output MIPI DSI RX0 data lane 3 positive.
16 RX0_DN3 output MIPI DSI RX0 data lane 3 negative.
17 VSS power_in Digital ground return.
18 IF_SEL1 input Interface selection signal bit 1; must be tied to VDDIO.
19 VDD_CORE power_in Digital core power supply, 1.2 V.
20 IF_SEL0 input Interface selection signal bit 0; must be tied to VSS.
21 VDDIO power_in I/O power supply, 1.8 V or 3.3 V.
22 VSS power_in Digital ground return.
23 VSS power_in Digital ground return.
24 VSS power_in Digital ground return.
25 RESET input System reset input, active-low. Tie to VDDIO when not used.
26 VDDIO power_in I/O power supply, 1.8 V or 3.3 V.
27 VDD_CORE power_in Digital core power supply, 1.2 V.
28 VSS power_in Digital ground return.
29 CSX input SPI chip select, active-low.
30 CLK_IN input Reserved clock input; leave open when not used.
31 PD_N input Power-down, active-low. Tie to VDDIO when not used.
32 NC unconnected No connect.
33 NC unconnected No connect.
34 NC unconnected No connect.
35 NC unconnected No connect.
36 NC unconnected No connect.
37 NC unconnected No connect.
38 NC unconnected No connect.
39 NC unconnected No connect.
40 NC unconnected No connect.
41 NC unconnected No connect.
42 NC unconnected No connect.
43 TE_OUT_0 output Output tearing-effect signal for DSI0; leave open when not used.
44 TE_OUT_1 output Output tearing-effect signal for DSI1; leave open when not used.
45 VDDIO power_in I/O power supply, 1.8 V or 3.3 V.
46 XTAL_IN input Crystal input for system PLL. Frequency range 8-30 MHz. Tie to VDDIO/GND when not used.
47 XTAL_OUT output Crystal output for system PLL; leave open when not used.
48 VSS power_in Digital ground return.
49 VDD_CORE power_in Digital core power supply, 1.2 V.
50 NC unconnected No connect.
51 NC unconnected No connect.
52 NC unconnected No connect.
53 NC unconnected No connect.
54 NC unconnected No connect.
55 NC unconnected No connect.
56 NC unconnected No connect.
57 NC unconnected No connect.
58 NC unconnected No connect.
59 NC unconnected No connect.
60 NC unconnected No connect.
61 NC unconnected No connect.
62 NC unconnected No connect.
63 NC unconnected No connect.
64 SDO output SPI serial data output; leave open when not used.
65 SDI input SPI serial data input.
66 SCK input SPI serial clock.
67 TE_IN_1 input Input tearing-effect signal for DSI1. Tie to VDDIO/GND when not used.
68 TE_IN_0 input Input tearing-effect signal for DSI0. Tie to VDDIO/GND when not used.
69 VSS power_in Digital ground return.
70 VDD_CORE power_in Digital core power supply, 1.2 V.
71 VDDIO power_in I/O power supply, 1.8 V or 3.3 V.
72 SDC input SPI data/command select (for 8-bit 4-wire mode).
73 PS4 input Interface selection PS[4] - reserved, tie to VDDIO.
74 PS3 input Interface selection PS[3] - reserved, tie to VDDIO.
75 PS2 input Interface selection PS[2] - reserved, tie to VDDIO.
76 PS1 input SPI mode select PS[1]; combined with PS[0] selects 3-wire 24-bit, 3-wire 8-bit, or 4-wire 8-bit SPI.
77 PS0 input SPI mode select PS[0]; combined with PS[1] selects SPI interface variant.
78 INT_B output Interrupt output; leave open when not used.
79 VDD_CORE power_in Digital core power supply, 1.2 V.
80 VSS power_in Digital ground return.
81 RX1_DN3 output MIPI DSI RX1 data lane 3 negative.
82 RX1_DP3 output MIPI DSI RX1 data lane 3 positive.
83 VSS power_in Digital ground return.
84 RX1_DN0 bidirectional MIPI DSI RX1 data lane 0 negative (LP bidirectional).
85 RX1_DP0 bidirectional MIPI DSI RX1 data lane 0 positive (LP bidirectional).
86 VSS power_in Digital ground return.
87 AVDD power_in Analog power supply, 1.2 V.
88 RX1_CN output MIPI DSI RX1 clock lane negative.
89 RX1_CP output MIPI DSI RX1 clock lane positive.
90 AVSS power_in Analog ground return.
91 RX1_DN1 output MIPI DSI RX1 data lane 1 negative.
92 RX1_DP1 output MIPI DSI RX1 data lane 1 positive.
93 VSS power_in Digital ground return.
94 RX1_DN2 output MIPI DSI RX1 data lane 2 negative.
95 RX1_DP2 output MIPI DSI RX1 data lane 2 positive.
96 AVDD power_in Analog power supply, 1.2 V.
97 AVDD_CDR power_in Analog regulator output for D-PHY CDR, 1.2 V.
98 TX1_DN3 output MIPI DSI TX1 data lane 3 negative.
99 TX1_DP3 output MIPI DSI TX1 data lane 3 positive.
100 TX1_DN0 bidirectional MIPI DSI TX1 data lane 0 negative (LP bidirectional).
101 TX1_DP0 bidirectional MIPI DSI TX1 data lane 0 positive (LP bidirectional).
102 VDRV power_in MIPI TX driver power (0.5 V); connect to VDRV_REG.
103 AVDD power_in Analog power supply, 1.2 V.
104 AVDD power_in Analog power supply, 1.2 V.
105 TX1_CN output MIPI DSI TX1 clock lane negative.
106 TX1_CP output MIPI DSI TX1 clock lane positive.
107 TX1_DN1 output MIPI DSI TX1 data lane 1 negative.
108 VDRV power_in MIPI TX driver power (0.5 V); connect to VDRV_REG.
109 TX1_DP1 output MIPI DSI TX1 data lane 1 positive.
110 TX1_DN2 output MIPI DSI TX1 data lane 2 negative.
111 TX1_DP2 output MIPI DSI TX1 data lane 2 positive.
112 AVDD power_in Analog power supply, 1.2 V.
113 VCIP power_in Bandgap power supply, 3.3 V.
114 VDRV_REG power_out Low-voltage regulator output; source for VDRV pins.
115 VSS power_in Digital ground return.
116 TX0_DN3 output MIPI DSI TX0 data lane 3 negative.
117 TX0_DP3 output MIPI DSI TX0 data lane 3 positive.
118 TX0_DN0 bidirectional MIPI DSI TX0 data lane 0 negative (LP bidirectional).
119 TX0_DP0 bidirectional MIPI DSI TX0 data lane 0 positive (LP bidirectional).
120 VDRV power_in MIPI TX driver power (0.5 V); connect to VDRV_REG.
121 AVDD power_in Analog power supply, 1.2 V.
122 TX0_CN output MIPI DSI TX0 clock lane negative.
123 TX0_CP output MIPI DSI TX0 clock lane positive.
124 TX0_DN1 output MIPI DSI TX0 data lane 1 negative.
125 VDRV power_in MIPI TX driver power (0.5 V); connect to VDRV_REG.
126 TX0_DP1 output MIPI DSI TX0 data lane 1 positive.
127 TX0_DN2 output MIPI DSI TX0 data lane 2 negative.
128 TX0_DP2 output MIPI DSI TX0 data lane 2 positive.

Key specifications

Parameter Value
Manufacturer Solomon Systech
Package LQFP-128(14x14)
Category Interface
Pins 128

Ordering variants

Same part, different packaging or reel option.

  • SSD2831QL9

CAD (KiCad official)

  • Symbol: SSD2831QL9
  • Footprint: Package_QFP:LQFP-128_14x14mm_P0.4mm
  • 3D model: LQFP-128(14x14) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Solomon Systech datasheet (173 pp, sha256 2b81b079075ddeb5, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF