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sr9900ai

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by Ray

CoreChips Ethernet Controllers, QFN-24-EP(4x4). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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SR9900AI

CoreChips · Ethernet Controllers · QFN-24-EP(4x4)

SR9900AI from CoreChips, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AVDD33 power_in 3.3 V analog supply input (3.14-3.46 V). Powers the Ethernet PHY analog front-end; decouple close to the pin.
2 MDI+[0] bidirectional Ethernet MDI pair 0 positive line. In MDI mode this pair is the receive channel; in MDIX (Auto-MDIX) mode it becomes the transmit channel. Connect to a 1:1 magnetics transformer.
3 MDI-[0] bidirectional Ethernet MDI pair 0 negative line. RX in MDI mode, TX in MDIX mode.
4 MDI+[1] bidirectional Ethernet MDI pair 1 positive line. TX in MDI mode, RX in MDIX mode.
5 MDI-[1] bidirectional Ethernet MDI pair 1 negative line. TX in MDI mode, RX in MDIX mode.
6 U2GND power_in USB transceiver ground return. Tie to system ground plane; keep the USB return path short.
7 U2DM bidirectional USB 2.0 / USB 1.1 differential data line D- (minus). Route as a 90 Ω differential pair with U2DP to the host connector.
8 U2DP bidirectional USB 2.0 / USB 1.1 differential data line D+ (plus). Route as a 90 Ω differential pair with U2DM.
9 DVDD12 power_in 1.2 V digital supply input for the USB module (1.08-1.32 V). Typically fed from the internal LDO output on pin 23 (AVDD12).
10 AVDD33 power_out 3.3 V regulated output from the on-chip LDO1 (nom 3.3 V, 3.14-3.46 V). Used when VDD5 supplies the chip; requires decoupling to ground. In 3.3 V-only designs (embedded market) VDD5 is left open and this pin is tied to the external 3.3 V rail.
11 VDD5 power_in 5 V supply input to the internal LDO1 (4.75-5.25 V, absolute max 5.5 V). Used in USB bus-powered / peripheral designs. Leave floating (open) in embedded 3.3 V-only designs, per the reference schematic.
12 DVDD12_UPS power_out 1.2 V standby/backup regulated output from LDO1 (1.08-1.32 V). Powers the always-on domain for wake-on-LAN and sleep-mode operation.
13 DVDD33 power_in 3.3 V digital supply input (3.14-3.46 V). Decouple to ground close to the pin.
14 GPIO bidirectional General-purpose I/O. 3.3 V CMOS levels (VIH ≥ 2.0 V, VIL ≤ 0.9 V), 8 mA drive; internal pull-up/pull-down ≈75 kΩ (40-150 kΩ). Can be strapped to disable the Ethernet function.
15 LED0/SPICSB output Muxed output: LED0 indicator drive (blink rate and duty cycle programmable) OR SPI Flash chip-select (active-low, SPICSB). Function is selected by the operating mode / OTP configuration.
16 DVDD12 power_in 1.2 V digital core supply input (1.08-1.32 V). Typically bridged to AVDD12 (pin 23) via ferrite/bulk cap network.
17 LED1/SPISCK output Muxed output: LED1 indicator drive OR SPI Flash serial clock (SPISCK). Function is selected by the operating mode / OTP configuration.
18 SPISDI output SPI Flash serial data input (from the chip's perspective this is MOSI - data driven OUT of SR9900AI INTO the SPI Flash's SDI/DI pin).
19 LANWAKEB output Power-management / wake event output, active-low. Asserted on link-status change, magic packet, or Microsoft wake pattern to wake the host over PME#/GPIO.
20 SPISDO input SPI Flash serial data output (from the chip's perspective this is MISO - data driven OUT of the SPI Flash's SDO/DO pin INTO SR9900AI).
21 XTAL1 input 25 MHz crystal input. Connect one terminal of a 25 MHz crystal here (with load cap to GND), or drive from a 25 MHz clock source (single-ended oscillator).
22 XTAL2 output 25 MHz crystal output. Connect the other terminal of the 25 MHz crystal here (with load cap to GND). Leave floating if XTAL1 is driven from an external oscillator.
23 AVDD12 power_out 1.2 V regulated output from the internal LDO2 (1.08-1.32 V) and 1.2 V analog supply input. Decouple to GND with a bulk + 0.1 µF cap; typically tied to DVDD12 (pins 9 and 16) via a filter network.
24 RSET passive PHY bias reference resistor. Connect a 2.49 kΩ 1 % resistor from this pin to GND to set the internal current reference.
25 GND power_in Exposed thermal / analog ground pad on the QFN underside. Must be soldered to the PCB ground plane for both electrical grounding and thermal dissipation.

Key specifications

Parameter Value
Manufacturer CoreChips
Package QFN-24-EP(4x4)
Category Interface
Pins 25

Ordering variants

  • SR9900AI

CAD (KiCad official)

  • Symbol: SR9900AI
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm
  • 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: CoreChips datasheet (None pp, sha256 153531cb1c1df4ac, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

Schematic Symbol

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PCB Footprint

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