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Contents

README

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SQJA72EP-T1_GE3

Vishay Intertech · MOSFETs · SO-8-4

SQJA72EP-T1_GE3 from Vishay Intertech, in a SO-8-4. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S passive Source terminal of the N-channel MOSFET. One of three source leads (pins 1, 2, 3) tied together on the PowerPAK SO-8L single package.
2 S passive Source terminal of the N-channel MOSFET. One of three source leads (pins 1, 2, 3) tied together on the PowerPAK SO-8L single package.
3 S passive Source terminal of the N-channel MOSFET. One of three source leads (pins 1, 2, 3) tied together on the PowerPAK SO-8L single package.
4 G input Gate terminal of the N-channel MOSFET. VGS(th) typ. 2.0 V (1.5 V min., 2.5 V max.); absolute maximum VGS = ±20 V. Drives the channel between drain and source.
5 D passive Drain terminal of the N-channel MOSFET, exposed as the large backside pad of the PowerPAK SO-8L package. VDS = 100 V max., continuous ID = 37 A at TC = 25 °C, RDS(on) = 19 mΩ at VGS = 10 V.

Key specifications

Parameter Value
Manufacturer Vishay Intertech
Package SO-8-4
Category Transistors/Thyristors
Pins 5

Ordering variants

Same part, different packaging or reel option.

  • SQJA72EP-T1_GE3

CAD (KiCad official)

  • Symbol: SQJA72EP-T1_GE3
  • Footprint: Package_SO:SO-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8-4 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Vishay Intertech datasheet (9 pp, sha256 79ef288272f8aea4, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF