component
sn74lvc74apwr
Public Unreviewedby Ray
Texas Instruments Flip Flops, TSSOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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README
markdownSN74LVC74APWR
Texas Instruments · Flip Flops · TSSOP-14
SN74LVC74APWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1CLR | input | Channel 1 asynchronous clear input (active low). Driving 1CLR low forces 1Q low and 1Q̄ high regardless of 1CLK or 1D. Overvoltage-tolerant to 5.5V. |
| 2 | 1D | input | Channel 1 data input. Latched into 1Q on the rising edge of 1CLK when 1PRE and 1CLR are both high. Overvoltage-tolerant to 5.5V. |
| 3 | 1CLK | input | Channel 1 clock input (positive-edge triggered). Data on 1D is transferred to 1Q on the rising edge, subject to setup/hold. fmax up to 100 MHz at 3.3V. Overvoltage-tolerant to 5.5V. |
| 4 | 1PRE | input | Channel 1 asynchronous preset input (active low). Driving 1PRE low forces 1Q high and 1Q̄ low regardless of 1CLK or 1D. Overvoltage-tolerant to 5.5V. |
| 5 | 1Q | output | Channel 1 non-inverted flip-flop output. Push-pull CMOS drive up to ±24 mA at VCC = 3V. Follows 1D on rising 1CLK when preset and clear are inactive. |
| 6 | 1Q̄ | output | Channel 1 inverted flip-flop output (complement of 1Q). Push-pull CMOS drive up to ±24 mA at VCC = 3V. |
| 7 | GND | power_in | Device ground reference (0V). |
| 8 | 2Q̄ | output | Channel 2 inverted flip-flop output (complement of 2Q). Push-pull CMOS drive up to ±24 mA at VCC = 3V. |
| 9 | 2Q | output | Channel 2 non-inverted flip-flop output. Push-pull CMOS drive up to ±24 mA at VCC = 3V. Follows 2D on rising 2CLK when preset and clear are inactive. |
| 10 | 2PRE | input | Channel 2 asynchronous preset input (active low). Driving 2PRE low forces 2Q high and 2Q̄ low regardless of 2CLK or 2D. Overvoltage-tolerant to 5.5V. |
| 11 | 2CLK | input | Channel 2 clock input (positive-edge triggered). Data on 2D is transferred to 2Q on the rising edge, subject to setup/hold. Overvoltage-tolerant to 5.5V. |
| 12 | 2D | input | Channel 2 data input. Latched into 2Q on the rising edge of 2CLK when 2PRE and 2CLR are both high. Overvoltage-tolerant to 5.5V. |
| 13 | 2CLR | input | Channel 2 asynchronous clear input (active low). Driving 2CLR low forces 2Q low and 2Q̄ high regardless of 2CLK or 2D. Overvoltage-tolerant to 5.5V. |
| 14 | VCC | power_in | Positive supply input. Recommended operating range 1.65V to 3.6V for SN74LVC74A. Requires a 0.1 µF bypass capacitor placed close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
Ordering variants
SN74LVC74APWRSN74LVC74APWRDSN74LVC74APWRDRSN74LVC74APWRDBSN74LVC74APWRDBRSN74LVC74APWRNSSN74LVC74APWRNSRSN74LVC74APWRBQASN74LVC74APWRBQARSN74LVC74APWRRGYSN74LVC74APWRRGYRSN74LVC74APWRJSN74LVC74APWRWSN74LVC74APWRFK
CAD (KiCad official)
- Symbol:
SN74LVC74APWR - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (None pp, sha256
96f7f1f405071e93, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).